CMOS basic cell and method for fabricating semiconductor integrated circuit using the same

A CMOS basic cell comprising:

• an N-channel transistor and a P-channel transistor existing on a semiconductor substrate, said CMOS basic cell being electrical coupled with other adjacent CMOS basic cells;
• wherein a gate of at least one of said N-channel transistor and said P-channel transistor has a hooked shape including a first bent part bending in one sideward direction at an upper portion thereof and a second bent part bending in an opposite sideward direction at a lower portion thereof, and
• a diffusion region of at least one of said N-channel transistor and said P-channel transistor having a hooked shape having a first bent part bending in one sideward direction at an upper portion thereof and a second bent part bending in an opposite sideward direction at a lower portion thereof,
• said upper portion of said gate is bent oppositely to said upper portion of said diffusion region.

A semiconductor integrated circuit including a plurality of CMOS basic cells arranged in the same direction,

• wherein each CMOS basic cell is composed of first and second N-channel transistors and first and second P-channel transistors, and
• a gate of said first and second N-channel transistors and said first and second P-channel transistors of each cell is in a hooked shape having a first bent part bending in one sideward direction at an upper portion thereof and a second bent part bending in the other sideward direction at a lower portion thereof,
• wherein the gates of said first and second N-channel transistors are disposed in a manner that said first bent part of one gate overlaps said second bent part of the other gate when viewed along an axis orthogonal to the axis extending parallel to the sideward directions in which said first bent part and said second bent part extend, and
• wherein the gates of said first and second P-channel transistors are disposed in a manner that said first bent part of one gate overlaps said second bent part of the other gate when viewed along an axis orthogonal to an axis extending parallel to the sideward directions in which said first bent part and said second bent part extend.

A semiconductor integrated circuit comprising:

• a plurality of CMOS basic cells;
• each said CMOS basic cell comprising:
• an interconnect layer formed in an uppermost layer of each of said plurality of CMOS basic cells, said interconnect layer comprising at least one interconnect operative for connecting signals to and from the corresponding CMOS basic cell;
• an N-channel transistor and a P-channel transistor on a semiconductor substrate;
• and
• an interconnect pattern which is capable of being electrically isolated from said N-channel transistor and said P-channel transistor and which is disposed between said N-channel transistor and said P-channel transistor,
• wherein said interconnect pattern is formed in said uppermost layer of said CMOS basic cell,
• wherein said interconnect pattern is only capable of being coupled to said N-channel transistor or said P-channel transistor by utilizing an interconnect pattern which is disposed in an interconnect layer located above said uppermost layer of said CMOS basic cell.

A CMOS basic cell comprising:

• an N-channel transistor and, a P-channel transistor on a semiconductor substrate;
• an interconnect pattern which is disposed between said N-channel transistor and said P-channel transistor;
• wherein said interconnect pattern is isolated from said N-channel transistor and said P-channel transistor;
• wherein said interconnect pattern is formed in an uppermost interconnect layer of said CMOS basic cell, and
• wherein said CMOS basic cell has a boundary defining the edges of the CMOS basic cell, and at least one end of said interconnect pattern does not contact any edge of said CMOS basic cell.

A CMOS basic cell comprising:

• an N-channel transistor and, a P-channel transistor on a semiconductor substrate;
• an interconnect pattern which is disposed between said N-channel transistor and said P-channel transistor,
• wherein said interconnect pattern is isolated from said N-channel transistor and said P-channel transistor,
• wherein said interconnect pattern is formed in an uppermost interconnect layer of said CMOS basic cell, and
• wherein said N-channel transistor and said P-channel transistor have a plurality of electrodes, and each electrode coupled to said N-channel transistor and said P-channel transistor is coupled to the uppermost layer of said CMOS basic cell via an interconnect.