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US 6,795,520 B2Granted
High speed digital counters
AssigneeZarlink Semiconductor Inc.
InventorRobertus Laurentius Van Der Valk
Life of this patent
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Abstract
A high speed digital counter consists of a chain of asynchronous counter cells. Each cell includes a flip-flop with a master latch and a slave latch and a clock gating circuit. The clock gating circuit derives an enable input from an output of the master latch.
Claims18
A high speed digital ripple counter comprising:
- a chain of counter cells comprising a first counter cell and a series of subsequent counter cells, each of said first counter cell and said subsequent counter cells comprising a flip-flop having a master latch and slave latch, each said master and slave latch being provided with data and gating inputs;
- each said subsequent counter cell including a gating circuit having an output supplying gated clock signals to the gating inputs of the master and slave latches associated with that counter cell;
- each said gating circuit of said subsequent counter cells having a first input connected to receive signals applied to the gating inputs of the preceding counter cell and an enable input connected to an output of the master latch of the preceding counter cell;
- and
- a clock input for providing clock signals to the gating inputs of said first counter cell.
2 more elements
Dependencies are inferred from the claim text.