Back to results
US 6,794,677 B2Granted
Semiconductor integrated circuit device and method for fabricating the same
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsTokuhiko Tamaki, Koichi Kawashima, Yasuo Sakurai, Kenji Tateiwa
Life of this patent
Estimating the term…
Abstract
Variations in the size of a linear pattern resulting from difference in mask pattern layout are prevented by setting the perimeter of the linear pattern per unit area in a specified range irrespective of the type of a semiconductor integrated circuit device or by adjusting a process condition in accordance with type-to-type difference in the perimeter of the linear pattern per unit area.
Claims6
A semiconductor integrated circuit device comprising:
- a first circuit pattern having a first linear pattern and placed in a region in which a group of elements having a repetitive pattern are formed;
- and
- a second circuit pattern having a second linear pattern and placed in a region in which components other than the group of elements are formed,
- a dummy pattern being inserted in the region in which the second circuit pattern is placed such that a sum perimeter of the first linear pattern, the second linear pattern, and the dummy pattern per unit area is equal to or less than a perimeter of the first linear pattern per unit area.
1 more element
A semiconductor integrated circuit device comprising:
- a first circuit pattern having a first gate electrode pattern and placed in a memory circuit region;
- and
- a second circuit pattern having a second gate electrode pattern and placed in a logic circuit region,
- a dummy pattern being inserted in the logic region in which the second circuit pattern is placed such that a sum perimeter of the first gate electrode pattern, the second gate electrode pattern, and the dummy pattern per unit area is equal to or less than a perimeter of the first gate electrode pattern per unit area.
1 more element
Dependencies are inferred from the claim text.