Pattern data generation system, method and program for pattern data generation, reticle fabricating method, and semiconductor device manufacturing method using the pattern data

A computer implemented method for pattern data generation comprising:

• generating chip division information by performing division processing of a chip pattern so that pattern data of enlarged reticle chip pattern data fit into a master mask pattern region;
• registering the chip division information in a chip division information storage unit;
• generating master mask chip layout information by sequentially allotting sub-patterns to a master mask in an order beginning with the largest from a plurality of sub-patterns configuring the chip division information;
• registering the master mask chip layout information in a master mask chip layout information storage unit;
• generating master mask chip pattern data by referencing the reticle chip pattern data and dividing each chip in accordance with the master mask chip layout data;
• registering the master mask chip pattern data in a master mask pattern data information storage unit;
• and
• generating master mask pattern data by referencing the master mask chip layout information and the master mask chip pattern data.

A computer program product for controlling a pattern data generation system, the program product comprising:

• a command for generating chip division information by dividing a chip pattern into a plurality of sub-patterns so that pattern data of enlarged reticle chip pattern data fit into a master mask pattern region;
• a command for registering the chip division information in a chip division information storage unit;
• a command for generating master mask chip layout information by sequentially allotting sub-patterns to a master mask in an order beginning with the largest from the plurality of sub-patterns;
• a command for registering the master mask chip layout information in a master mask chip layout information storage unit;
• a command for generating master mask chip pattern data by referencing the reticle chip pattern data and dividing each chip in accordance with the master mask chip layout data;
• a command for registering the master mask chip pattern data in a master mask pattern data information storage unit;
• and
• a command for generating master mask pattern data by referencing the master mask chip layout information and the master mask chip pattern data.

A method for fabricating reticles comprising:

• designing a planar pattern on the surface of a semiconductor chip;
• determining chip pattern data for a necessary number of respective reticles for achieving a planar pattern upon the semiconductor chip;
• generating chip division information by dividing a chip pattern into a plurality of sub-patterns so that pattern data of enlarged chip pattern data for the respective reticles fit into a master mask pattern region;
• generating master mask chip layout information by selecting a sub-pattern in an order beginning with the largest from the plurality of sub-patterns and sequentially allotting sub-patterns to a master mask;
• generating master mask chip pattern data by referencing the chip pattern data for the reticle and dividing each chip in accordance with the master mask chip layout data;
• generating master mask pattern data by referencing the master mask chip layout information and the master mask chip pattern data;
• obtaining a plurality of master masks by respectively pattern a master mask upon a plurality of master mask substrates in accordance with the generated master mask pattern data by a pattern generator;
• and
• generating the necessary number of respective reticles through the reduction/transcription of the master mask by an exposure system.

A method for manufacturing a semiconductor device comprising:

• designing a planar pattern on the surface of a semiconductor chip;
• determining chip pattern data for a necessary number of respective reticles for achieving
• a planar pattern upon the semiconductor chip;
• generating chip division information by dividing a chip pattern into a plurality of sub-patterns so that pattern data of enlarged chip pattern data for the respective reticles fit into a master mask pattern region;
• generating master mask chip layout information by selecting a sub-pattern in an order beginning with the largest of the plurality of sub-patterns and sequentially allotting sub-patterns to a master mask;
• generating master mask chip pattern data by referencing the chip pattern data for the reticle and dividing each chip in accordance with the master mask chip layout data;
• generating master mask pattern data by referencing the master mask chip layout information and the master mask chip pattern data;
• obtaining a plurality of master masks by respectively patterning a master mask upon a plurality of master mask substrates in accordance with the generated master mask pattern data by a pattern generator;
• generating the necessary number of respective reticles through the reduction/transcription of the master mask by an exposure system;
• and
• forming a desired microscopic pattern upon a semiconductor substrate through a sequence of manufacturing steps including a selective diffusion step where a diffusion mask provided through photolithography step using one of the necessary number of reticles is used, and a selective etching step where an etch mask provided through photolithography using another one of the necessary number of reticles.