US 6,787,875 B2 · Self-aligned vias in an integrated circuit structure

Abstract

A method of forming a via in an integrated circuit is provided. The method includes forming a stack including a first layer, a hard mask layer, and at least one intermediate layer disposed between the first layer and the hard mask layer. The first layer comprises a first metal line. The method further includes forming a channel in the hard mask layer. The channel has a first side and a second side opposite the first side. The method further includes forming a resist layer having an opening extending over both the first and second sides of the channel. The method further includes forming a metal line trench and a via opening aligned with the first and second sides of the channel. The method further includes filling the filling the metal line trench and the via opening with a conductive material to create a second metal line and a via connecting the second metal line with the first metal line.

Claims16

Dependent claims

A method of forming a via in an integrated circuit, comprising:

forming a stack including a first layer, a hard mask layer, and at least one intermediate layer disposed between the first layer and the hard mask layer, the first layer including a first metal line;
forming a channel in the hard mask layer, the channel having a first side and a second side opposite the first side;
forming a resist layer having an opening extending over both the first and second sides of the channel;
forming a metal line trench and a via opening aligned with the first and second sides of the channel;
and
filling the metal line trench and the via opening with a conductive material to create a second metal line and a via connecting the second metal line with the first metal line.

3 more elements

A method of forming a via in an integrated circuit, comprising:

forming a stack including a first layer, a hard mask layer, and at least one intermediate layer disposed between the first layer and the hard mask layer, the first layer comprising a first metal line and a second metal line;
forming a first channel and a second channel in the hard mask layer, each channel having a first side and a second side opposite the first side;
forming a resist layer having a first open region extending over the first and second sides of the first channel and a second open region extending over the first and second sides of the second channel;
forming a first metal line trench and via opening aligned with the first and second sides of the first channel and a second metal line trench and via opening aligned with the first and second sides of the second channel;
filling the first metal line trench and via opening to create a third metal line and a first via connecting the third metal line with the first metal line;
and
filling the second metal line trench and via opening to create a fourth metal line and a second via connecting the fourth metal line with the second metal line.

4 more elements

Dependencies are inferred from the claim text.

Self-aligned vias in an integrated circuit structure

Life of this patent

Self-aligned vias in an integrated circuit structure

Life of this patent

Abstract

Claims16