Apparatus and method for inhibiting dummy cell over erase
AssigneeMacronix International Co., Ltd.
InventorsJen-Ren Huang, Ming-Hung Chou
Life of this patent
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Abstract
A semiconductor device that includes a semiconductor substrate including a memory cell region and a dummy cell region, a plurality of substantially parallel bit lines in the semiconductor substrate, a plurality of memory cell gate dielectrics provided over the bit lines in the memory cell region, the memory cell gate dielectrics comprising an oxide-nitrideoxide (ONO) layer, a plurality of dummy cell gate dielectrics provided over the plurality of bit lines in the dummy cell region, wherein the dummy cell gate dielectrics is non-trapping for electric charges, and a plurality of substantially parallel word lines over the memory cell gate dielectrics and the dummy cell gate dielectrics.
Claims18
A semiconductor device, comprising:
- a semiconductor substrate including a memory cell region and a dummy cell region;
- a plurality of substantially parallel bit lines in the semiconductor substrate;
- a plurality of memory cell gate dielectrics provided over the bit lines in the memory cell region, the memory cell gate dielectrics comprising an oxide-nitride-oxide (ONO) layer;
- a plurality of dummy cell gate dielectrics provided over the plurality of bit lines in the dummy cell region, wherein the dummy cell gate dielectrics is non-trapping for electric charges;
- and
- a plurality of substantially parallel word lines over the memory cell gate dielectrics and the dummy cell gate dielectrics.
A method for manufacturing a semiconductor device, comprising:
- providing a semiconductor substrate;
- providing a memory cell region and a dummy cell region in the semiconductor substrate;
- forming a plurality of bit lines in the semiconductor substrate;
- providing an oxide-nitride-oxide layer over the plurality of bit lines in the memory cell region;
- providing a layer of non-trapping material over the plurality of bit lines in the dummy cell region, wherein the non-trapping material comprises an oxide;
- and
- providing a plurality of word lines over the oxide-nitride-oxide layer and the layer of non-trapping material in the memory cell region and the dummy cell region.
A method for manufacturing a semiconductor device, comprising:
- providing a semiconductor substrate;
- providing a memory cell region and a dummy cell region in the semiconductor substrate;
- forming at least one memory cell in the memory cell region, including
- providing a first source region and a first drain region in the semiconductor substrate,
- providing an oxide-nitride-oxide layer over the first source and drain regions,
- patterning and etching the oxide-nitride-oxide layer to form at least one gate dielectric, and
- providing a first gate over the at least one gate dielectric;
- and
- forming at least one dummy cell in the dummy cell region, including
- providing a second source region and a second drain region in the semiconductor substrate,
- providing a layer of non-trapping material over the second source and drain regions, wherein the non-trapping material comprises one of silicon dioxide and aluminum oxide,
- patterning and etching the layer of non-trapping material to form at least one dummy gate dielectric, and
- providing a second gate over the layer of non-trapping material.
Dependencies are inferred from the claim text.