Carrier injection protection structure

An integrated circuit comprised of:

• a resistive substrate;
• a power transistor formed on said substrate, wherein said power transistor includes a drain;
• a digital logic array formed on said substrate next to said power transistor;
• low resistivity means to collect minority carriers injected by said drain into said substrate, wherein said low resistivity means is formed on said substrate between said power transistor and said digital logic array;
• and
• recombination means to reduce the amount of minority carriers injected by said drain into said substrate, said recombination means formed in said substrate below said digital logic array;
• minority carrier collection means to extract minority carriers from said substrate, said minority carrier collection means formed in said substrate between said recombination means and said digital logic array.

A process for shielding a logic array from minority carrier injection into a substrate comprising the steps of:

• attenuating said injected minority carriers with a resistive substrate;
• collecting said injected minority carriers with a low resistivity ring formed in said resistive substrate;
• recombining said injected minority carriers with a region of high majority carrier concentration formed in said substrate under said logic array;
• and
• extracting said injected minority carriers from said substrate with a low resistivity region formed under said logic array.

A structure for protecting a logic array from a substrate minority carrier injection caused by inductive switching of a power device, comprised of:

• a substrate;
• a ring formed on said substrate, wherein said ring forms a low resistance path to ground for said minority carriers;
• a buried layer forms a region of high minority carrier recombination, wherein said buried layer formed in said substrate under said logic array;
• a low resistance buried region, said low resistance buried region provides a low resistance path to ground for minority carriers, said low resistance buried region formed under said logic array above said buried layer.