Contact structure a semiconductor device and manufacturing method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsHong Ki Kim, Duck Hyung Lee
Life of this patent
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Abstract
A semiconductor contact structure for a merged dynamic random access memory and a logic circuit (MDL) and a method of manufacturing the contact structure to: (i) a cell contact pad; (ii) at least one active region; and (iii) at least one gate electrode simultaneously, whereby an electric short between the gate electrodes and the cell contact pad is avoided, even in the event a lithographic misalignment occurs and whereby it is possible to obtain an overlap margin in the cell region, even with an improved metal contact to the gate electrode in the peripheral circuit region of the semiconductor device.
Claims5
A semiconductor device having a cell region and a peripheral region, each region having at least an active region, the semiconductor device comprising:
- a first conductivity type FET formed in the peripheral region;
- a second conductivity type FET formed in the peripheral region;
- cell transistors formed in the cell region:
- and
- a silicon oxide layer formed on a surface of an active region where the first conductivity type FET is formed,
- wherein the silicon oxide layer is not formed on a surface of an active region where the second conductivity type FET is formed, and
- wherein the cell transistors comprise a gate structure including a conductive layer and a capping insulation layer stacked on the conductive layer and the first and second conductivity type FETs do not comprise the capping insulation layer.
Dependencies are inferred from the claim text.