Semiconductor devices including a silicon-on-insulator layer
AssigneeSeiko Epson Corporation
InventorMichiru Hogyoku
Life of this patent
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Abstract
A semiconductor device in accordance with one example of the present invention pertains to a semiconductor device to be used for a CMOS inverter circuit, comprising a BOX layer 2 formed on a silicon substrate 1, a SOI film 3 including single crystal Si formed on the BOX layer, a gate oxide film 4 formed on the SOI film 3, a gate electrode 5 formed on the gate oxide film, and diffusion layers 7, 8 for source/drain regions formed in source/drain regions of the SOI film 3, wherein, when a power supply voltage of 0.6 V is used, a thickness TSOI of the SOI film 3 is 0.084 μm or greater and 0.094 μm or smaller, and an impurity concentration of the SOI film is 7.95×1017/cm3 or greater and 8.05×1017/cm3 or smaller.
Claims18
A semiconductor device to be used for a CMOS inverter circuit, the semiconductor device comprising:
- a dielectric film formed on a semiconductor substrate;
- a SOI film comprising single crystal Si formed on the dielectric layer film;
- a gate dielectric film formed on the SOI film;
- a gate electrode formed on the gate dielectric film;
- and
- a diffusion layer for source/drain regions formed in source/drain regions of the SOI film,
- wherein, when a power supply voltage of 0.6 V is used,
- a thickness of the SOI film is 0.084 μm or greater and 0.094 μm or smaller, and an impurity concentration of the SOI film is 7.95×1017/cm3 or greater and 8.05×1017/cm3 or smaller.
A semiconductor device to be used for a CMOS inverter circuit, the semiconductor device comprising:
- a dielectric film formed on a semiconductor substrate;
- a SOI film comprising single crystal Si formed on the dielectric layer film;
- a gate dielectric film formed on the SOI film;
- a gate electrode formed on the gate dielectric film;
- and
- a diffusion layer for source/drain regions formed in source/drain regions of the SOI film,
- wherein, when a power supply voltage of 0.6 V is used,
- a thickness of the SOI film is 0.089 μm or greater and 0.099 μm or smaller, and an impurity concentration of the SOI film is 8.95×1017/cm3 or greater and 9.05×1017/cm3 or smaller.
A semiconductor device to be used for a CMOS inverter circuit, the semiconductor device comprising:
- a dielectric film formed on a semiconductor substrate;
- a SOI film comprising single crystal Si formed on the dielectric layer film;
- a gate dielectric film formed on the SOI film;
- a gate electrode formed on the gate dielectric film;
- and
- a diffusion layer for source/drain regions formed in source/drain regions of the SOI film,
- wherein, when a power supply voltage of 0.6 V is used,
- a thickness of the SOI film is 0.093 μm or greater and 0.103 μM or smaller, and an impurity concentration of the SOI film is 0.095×1018/cm3 or greater and 1.005×1018/cm3 or smaller.
A semiconductor device to be used for a CMOS inverter circuit, the semiconductor device comprising:
- a dielectric film formed on a semiconductor substrate;
- a SOI film comprising single crystal Si formed on the dielectric layer film;
- a gate dielectric film formed on the SOI film;
- a gate electrode formed on the gate dielectric film;
- and
- a diffusion layer for source/drain regions formed in source/drain regions of the SOI film,
- wherein, when a power supply voltage of 0.6 V is used,
- a thickness of the SOI film is, 0.096 μm or greater and 0.106 μm or smaller, and an impurity concentration of the SOI film is 1.095×1018/cm3 or greater and 1.105×1018/cm3 or smaller.
A semiconductor device to be used for a CMOS inverter circuit, the semiconductor device comprising:
- a dielectric film formed on a semiconductor substrate;
- a SOI film comprising single crystal Si formed on the dielectric layer film;
- a gate dielectric film formed on the SOI film;
- a gate electrode formed on the gate dielectric film;
- and
- a diffusion layer for source/drain regions formed in source/drain regions of the SOI film,
- wherein, when a power supply voltage of 0.6 V is used,
- a thickness of the SOI film is 0.100 μm or greater and 0.110 m or smaller, and an impurity concentration of the SOI film is 1.195×1018/cm3 or greater and 1.205×1018/cm3 or smaller.
A semiconductor device to be used for a CMOS inverter circuit, the semiconductor device comprising:
- a dielectric film formed on a semiconductor substrate;
- a SOI film comprising single crystal Si formed on the dielectric layer film;
- a gate dielectric film formed on the SOI film;
- a gate electrode formed on the gate dielectric film;
- and
- a diffusion layer for source/drain regions formed in source/drain regions of the SOI film,
- wherein, when a power supply voltage of 0.8 V is used,
- a thickness of th SOI film is 0.068 μm or greater and 0.078 μm or smaller, and an impurity concentration of the SOI film is 7.95×1017/cm3 or greater and 8.05×1017/cm3 or smaller.
A semiconductor device to be used for a CMOS inverter circuit, the semiconductor device comprising:
- a dielectric film formed on a semiconductor substrate;
- a SOI film comprising single crystal Si formed on the dielectric layer film;
- a gate dielectric film formed on the SOI film;
- a gate electrode formed on the gate dielectric film;
- and
- a diffusion layer for source/drain regions formed in source/drain regions of the SOI film,
- wherein, when a power supply voltage of 0.8 V is used,
- a thickness of the SOI film is 0.074 μm or greater and 0.084 μm or smaller, and an impurity concentration of the SOI film is 8.95×1017/cm3 or greater and 9.05×1017/cm3 or smaller.
A semiconductor device to be used for a CMOS inverter circuit, the semiconductor device comprising:
- a dielectric film formed on a semiconductor substrate;
- a SOI film comprising single crystal Si formed on the dielectric layer film;
- a gate dielectric film formed on the SOI film;
- a gate electrode formed on the gate dielectric film;
- and
- a diffusion layer for source/drain regions formed in source/drain regions of the SOI film,
- wherein, when a power supply voltage of 0.8 V is used,
- a thickness of the SOI film is 0.078 μm or greater and 0.088 μm or smaller, and an impurity concentration of the SOI film is 0.095×1018/cm3 or greater and 1.005×1018/cm3 or smaller.
A semiconductor device to be used for a CMOS inverter circuit, the semiconductor device comprising:
- a dielectric film formed on a semiconductor substrate;
- a SOI film comprising single crystal Si formed on the dielectric layer film;
- a gate dielectric film formed on the SOI film;
- a gate electrode formed on the gate dielectric film;
- and
- a diffusion layer for source/drain regions formed in source/drain regions of the SOI film,
- wherein, when a power supply voltage of 0.8 V is used,
- a thickness of the SOI film is 0.083 μm or greater and 0.093 μm or smaller, and an impurity concentration of the SOI film is 1.095×1018/cm3 or greater and 1.105×1018/cm3 or smaller.
A semiconductor device to be used for a CMOS inverter circuit, the semiconductor device comprising:
- a dielectric film formed on a semiconductor substrate;
- a SOI film comprising single crystal Si formed on the dielectric layer film;
- a gate dielectric film formed on the SOI film;
- a gate electrode formed on the gate dielectric film;
- and
- a diffusion layer for source/drain regions formed in source/drain regions of the SOI film,
- wherein, when a power supply voltage of 0.8 V is used,
- a thickness of the SOI film is 0.087 μm or greater and 0.097 μm or smaller, and an impurity concentration of the SOI film is 1.195×1018/cm3 or greater and 1.205×1018/cm3 or smaller.
A semiconductor device to be used for a CMOS inverter circuit, the semiconductor device comprising:
- a dielectric film formed on a semiconductor substrate;
- a SOI film comprising single crystal Si formed on the dielectric layer film;
- a gate dielectric film formed on the SOI film;
- a gate electrode formed on the gate dielectric film;
- and
- a diffusion layer for source/drain regions formed in source/drain regions of the SOI film,
- wherein, when a power supply voltage of 1.0 V is used,
- a thickness of the SOI film is 0.057 μm or greater and 0.067 μm or smaller, and an impurity concentration of the SOI film is 7.95×1017/cm3 or greater and 8.05×1017/cm3 or smaller.
A semiconductor device to be used for a CMOS inverter circuit, the semiconductor device comprising:
- a dielectric film formed on a semiconductor substrate;
- a SOI film comprising single crystal Si formed on the dielectric layer film;
- a gate dielectric film formed on the SOI film;
- a gate electrode formed on the gate dielectric film;
- and
- a diffusion layer for source/drain regions formed in source/drain regions of the SOI film,
- wherein, when a power supply voltage of 1.0 V is used,
- a thickness of the SOI film is 0.063 μm or greater and 0.073 μm or smaller, and an impurity concentration of the SOI film is 8.95×1017/cm3 or greater and 9.05×1017/cm3 or smaller.
A semiconductor device to be used for a CMOS inverter circuit, the semiconductor device comprising:
- a dielectric film formed on a semiconductor substrate;
- a SOI film comprising single crystal Si formed on the dielectric layer film;
- a gate dielectric film formed on the SOI film;
- a gate electrode formed on the gate dielectric film;
- and
- a diffusion layer for source/drain regions formed in source/drain regions of the SOI film,
- wherein, when a power supply voltage of 1.0 V is used,
- a thickness of the SOI film is 0.068 μm or greater and 0.078 μm or smaller, and an impurity concentration of the SOI film is 0.095×1018/cm3 or greater and 1.005×1018/cm3 or smaller.
A semiconductor device to be used for a CMOS inverter circuit, the semiconductor device comprising:
- a dielectric film formed on a semiconductor substrate;
- a SOI film comprising single crystal Si formed on the dielectric layer film;
- a gate dielectric film formed on the SOI film;
- a gate electrode formed on the gate dielectric film;
- and
- a diffusion layer for source/drain regions formed in source/drain regions of the SOI film,
- wherein, when a power supply voltage of 1.0 V is used,
- a thickness of the SOI film is 0.072 μm or greater and 0.082 μm or smaller, and an impurity concentration of the SOI film is 1.095×1018/cm3 or greater and 1.005×1018/cm3 or smaller.
A semiconductor device to be used for a CMOS inverter circuit, the semiconductor device comprising:
- a dielectric film formed on a semiconductor substrate;
- a SOI film comprising single crystal Si formed on the dielectric layer film;
- a gate dielectric film formed on the SOI film;
- a gate electrode formed on the gate dielectric film;
- and
- a diffusion layer for source/drain regions formed in source/drain regions of the SOI film,
- wherein, when a power supply voltage of 1.0 V is used,
- a thickness of the SOI film is 0.076 μm or greater and 0.086 μm or smaller, and an impurity concentration of the SOI film is 1.195×1018/cm3 or greater and 1.205×1018/cm3 or smaller.
Dependencies are inferred from the claim text.