Nonvolatile semiconductor memory cell and associated semiconductor circuit configuration and method for the fabrication of the circuit configuration
AssigneeInfineon Technologies AG
InventorGeorg Tempel
Life of this patent
Estimating the term…
Abstract
A nonvolatile semiconductor memory cell, an associated semiconductor circuit configuration and also a fabrication method, in which, in a substrate, active regions are formed with a first insulating layer situated above them, a charge-storing layer, a second insulating layer and a control layer. In order to realize a particularly small cell area, in a third insulating layer situated thereabove, openings are formed above at least partial regions of source/drain regions, which are each directly contact-connected via the openings by source and drain lines formed on an insulating web.
Claims21
A nonvolatile semiconductor memory cell, comprising:
- a substrate;
- an active region formed in said substrate and serving to define source/drain regions;
- a first insulating layer formed on said substrate;
- a charge-storing layer formed on said first insulating layer;
- a second insulating layer formed on said charge-storing layer;
- a control layer formed on said second insulating layer and defining word line stacks;
- an insulating protective layer surrounding at least said word line stacks;
- a third insulating layer formed over a whole area on said substrate and said word line stacks, said third insulating layer having openings formed therein;
- and
- at least one insulating web having sidewalls formed on said third insulating layer and serving to define at least one bit line with a source line and a drain line at at least one of said sidewalls, said source and drain lines each directly making contact with said source/drain regions through said openings in said third insulating layer.
A nonvolatile semiconductor circuit configuration having a multiplicity of semiconductor memory cells disposed in a matrix form, comprising:
- a substrate;
- active regions formed in said substrate and serving to define source/drain regions;
- a first insulating layer formed on said substrate;
- a charge-storing layer formed on said first insulating layer;
- a second insulating layer formed on said charge-storing layer;
- control layers formed on said second insulating layer and defining word line stacks, said control layers disposed in a row form;
- an insulating protective layer surrounding at least said word line stacks;
- a third insulating layer formed over a whole area on said substrate and said word line stacks, said third insulating layer having openings formed therein, said openings substantially disposed in zigzag form such that said active regions being at least partially uncovered;
- and
- insulating webs having sidewalls formed on said third insulating layer and serving to define bit lines with source lines and drain lines at at least one of said sidewalls, said source and drain lines each directly making contact with said source/drain regions through said openings in said third insulating layer, said active regions, said insulating webs and said respective ones of said source and drain lines disposed in column form.
A method for fabricating a semiconductor circuit configuration, which comprises the steps of:
- providing a substrate;
- forming substantially straight active regions in the substrate;
- forming a first insulating layer on the substrate;
- forming charge-storing layer on the first insulating layer;
- patterning the charge-storing layer in an x direction;
- forming a second insulating layer on the charge-storing layer;
- forming a control layer on the second insulating layer;
- forming a partial protective layer on the control layer;
- patterning the partial protective layer, the control layer, the second insulating layer and the charge-storing layer in a y direction for forming substantially straight word line stacks;
- forming source/drain regions in the active region of the substrate;
- forming spacers on sidewalls of the word line stacks;
- removing areas of the first insulating layer that are not covered;
- forming whole-area wide a third insulating layer on the substrate;
- forming openings in the third insulating layer for uncovering at least partially the active regions;
- forming an insulating web layer on the third insulating layer;
- patterning the insulating web layer in the y direction for forming insulating webs;
- forming a bit line layer;
- and
- shaping the bit line layer for forming source and drain lines on sidewalls of the insulating webs.
Dependencies are inferred from the claim text.