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US 6,787,838 B1Granted
Trench capacitor DRAM cell using buried oxide as array top oxide
AssigneeInternational Business Machines Corporation
InventorsDureseti Chidambarrao, Ramachandra Divakaruni, Deok-kee Kim
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Abstract
A trench capacitor DRAM cell in an SOI wafer uses the silicon device layer in the array as part of passing wordlines, stripping the silicon device layer in the array outside the wordlines and uses the BOX layer as the array top oxide separating the passing wordlines from the substrate.
Claims8
An integrated circuit comprising a DRAM array in an SOI wafer comprising:
- an SOI substrate having a device layer of silicon separated from a bulk substrate by a BOX layer, said device layer comprising an array area and a logic area outside the array area;
- a set of deep trenches in the array area having capacitors formed therein;
- a set of vertical transistors in the array disposed below the BOX;
- and
- a set of gate/wordline structures in the array arranged with wordlines insulated from the substrate by a dielectric.
2 more elements
Dependencies are inferred from the claim text.