Semiconductor device including evaluation elements
AssigneeNEC Electronics Corporation
InventorShinji Yokogawa
Life of this patent
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Abstract
In a semiconductor device including evaluation elements comprising a plurality of first wirings composed of a first wiring layer, a plurality of second wirings composed of a second wiring layer and vias connecting the first wirings and the second wirings, the first wirings and the second wirings are formed in directions almost perpendicular with each other, and relative to the plurality of first wirings juxtaposed with a prescribed interval, the plurality of second wirings connecting the adjacent first wirings are juxtaposed in the length direction of the first wirings, and a plurality of current paths are formed in parallel.
Claims2
In a semiconductor device including evaluation elements comprising a plurality of first wirings composed of a first wiring layer, a plurality of second wirings composed of a second wiring layer and via-holes (vias for short) connecting said first wirings and said second wirings, the semiconductor device including evaluation elements wherein
- said first wirings and said second wirings are formed respectively in directions almost perpendicular with each other, and
- relative to the plurality of said first wirings juxtaposed with a prescribed spacing, the plurality of said second wirings that connect said adjacent first wirings are juxtaposed in the length direction of said first wirings, and a plurality of current paths are formed in parallel.
Dependencies are inferred from the claim text.