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US 6,787,454 B1Granted
Method of manufacturing semiconductor device having dual damascene structure
AssigneeRenesas Technology Corp.
InventorTakayuki Saito
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Abstract
A via hole is formed to reach a Cu interconnection through an interlayer insulating film that covers the Cu interconnection. A conductive polymeric member is buried in the via hole electrolytically. A resist pattern is formed on the interlayer insulating film by photolithography, and a trench is formed, connected to the via hole, by etching, using the resist pattern as a mask. The resist pattern and the conductive polymeric member are removed thereafter.
Claims6
A method of manufacturing a semiconductor device having a dual damascene structure, comprising:
- forming a via hole which reaches an underlying interconnection through an interlayer insulating film that covers the underlying interconnection;
- forming a conductive polymeric member in the via hole electrolytically;
- forming a resist pattern on the interlayer insulating film after forming the conductive polymeric member;
- and
- forming a trench connected to the via hole by etching the interlayer insulating film using the resist pattern as a mask.
2 more elements
Dependencies are inferred from the claim text.