Method of forming an embedded memory including forming three silicon or polysilicon layers

A method of forming an embedded memory comprising the following steps:

• providing a semiconductor wafer, the semiconductor wafer comprising a substrate defined with a memory region and a peripheral region, the memory region comprising at least one cell-well and the peripheral region comprising at least one N-well and at least one P-well;
• forming an ONO layer, a first silicon layer, and a first dielectric layer in sequence on the semiconductor wafer covering the memory region and the peripheral region;
• performing a first photo-etching process to remove the first dielectric layer, the first silicon layer and the ONO layer in the peripheral region;
• forming at least one gate oxide layer in the peripheral region on the surface of the substrate;
• performing a chemical vapor deposition process to form a second silicon layer covering the surface of the semiconductor wafer;
• performing a second photo-etching process to remove the second silicon layer and the first dielectric layer in the memory region;
• forming at least a third silicon layer covering the memory region and the peripheral region on the surface of the semiconductor wafer;
• performing a third photo-etching process to form a first gate, a second gate, and a third gate above each of the cell-well, the N-well, and the P-well;
• performing a first ion implantation process to form a first drain and a first source at two sides of the first gate respectively;
• performing a second ion implantation process to form a second source and a second drain at two sides of the second gate respectively;
• and
• performing a third ion implantation process to form a third source and a third drain at two sides of the third gate respectively.