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US 6,787,416 B2Granted
Non volatile embedded memory with poly protection layer
AssigneeMacronix International Co., Ltd.
InventorsTung-Cheng Kuo, Chien-Hung Liu, Shyi-Shuh Pan, Shou-Wei Hung
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Abstract
The present invention includes devices and methods to form non-volatile memory cells and peripheral devices, with reduced damage to the electron trapping layer and, optionally, reduced thermal exposure during CMOS processing. Particular aspects of the present invention are described in the claims, specification and drawings.
Claims9
A method for fabricating a non-volatile memory and periphery devices, comprising:
- providing a substrate having a memory cell region and a periphery region;
- forming a charge trapping layer over at least part of the memory cell region;
- forming a first gate layer over at least part of the charge trapping layer;
- forming at least a gate oxide and a second gate layer in the periphery region;
- and then
- patterning the first gate layer to form a plurality of memory gates,
- further including forming a plurality of bit lines in both the periphery and cell regions, including;:
- implanting a first dopant in the substrate;
- forming sidewall spacers;
- and
- implanting a second dopant between the spacers to form a plurality of ladder bit lines.
8 more elements
Dependencies are inferred from the claim text.