US 6,787,408 B2 · Method for forming an electrical insulating layer on bit lines of the flash memory

Abstract

A method for forming an electrical insulating layer on bit lines of the flash memory is disclosed. A conductive layer, a mask layer and a cap layer are sequentially formed on a semiconductor substrate and then are etched to form a plurality of spacing. Afterwards, a dielectric layer is formed on the semiconductor substrate and a planarized layer is then formed on the dielectric layer. The planarized layer and the dielectric layer are etched sequentially wherein the etching rate of the planarized layer is less than that of the dielectric layer. Next, the dielectric layer is etched to remove a portion of the dielectric layer wherein the etching rate of the dielectric layer is higher than that of the cap layer, and thus a spacing dielectric layer is formed on the spacing. Thereafter, the cap layer is stripped wherein the etching rate of the dielectric layer is less than that of the mask layer so that the spacing dielectric layer has a round top and slant sides. Finally, the mask layer is stripped and then the spacing dielectric layer remains to form the electrical insulating layer on bit lines of the flash memory.

Claims20

Dependent claims

A method for forming an electrical insulating layer on bit lines of the flash memory, the method comprising the steps of:

providing a semiconductor substrate having a plurality of gate stacks wherein each of said gate stacks comprises a conductive layer, a mask layer and a cap layer, and a plurality of spacing are located between said gate stacks;
forming a dielectric layer on said gate stacks to fills into said spacing wherein said dielectric layer is higher than said cap layer;
forming a planarized layer on said dielectric layer to generate a planar surface;
performing a first etching step to totally remove said dielectric layer on said cap layer and simultaneously forming a spacing dielectric layer on said spacing;
performing a second etching step to remove said cap layer wherein the etching rate of said dielectric layer is less than that of said mask layer so that said spacing dielectric layer has a round top and slant sides to prevent a thin film from stress concentration;
and
removing said mask layer and then remaining said spacing dielectric layer to form said electrical insulating layer.

4 more elements

Dependencies are inferred from the claim text.

Method for forming an electrical insulating layer on bit lines of the flash memory

Life of this patent

Method for forming an electrical insulating layer on bit lines of the flash memory

Life of this patent

Abstract

Claims20