Wafer carrier, wafer carrier components, and CMP system for polishing a semiconductor topography
AssigneeCypress Semiconductor Corporation
InventorRuediger Held
Life of this patent
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AssigneeCypress Semiconductor Corporation
InventorRuediger Held
Estimating the term…
A CMP system, a wafer carrier, and components of a wafer carrier are provided for processing a semiconductor topography. In particular, a CMP system, a wafer carrier, and components of a wafer carrier are provided in which a greater pressure may be applied in a first portion of a semiconductor topography than in a second portion of the topography. The first portion may, for example, be adjacent to an outer edge of the topography, while the second portion may include the center of the topography. Alternatively, the first portion and second portion of the semiconductor topography may include any region of the topography. The wafer carrier components may include a carrier plate and/or a carrier backing film adapted to apply a greater pressure in a first portion of the semiconductor topography than in a second portion of the semiconductor topography.
A wafer carrier for polishing a semiconductor topography, wherein the wafer carrier comprises:
A chemical-mechanical polishing system comprising:
A carrier plate for use in a chemical-mechanical polishing system, wherein said plate is dimensioned to apply a greater pressure in a first portion of a semiconductor topography than in a second portion of the semiconductor topography when the topography is pressed against a polishing pad such that the first portion of the topography is polished at a faster rate than the second portion of the topography, wherein the carrier plate comprises a recessed portion having lateral dimensions approximately equal to lateral dimensions of the second portion, and wherein a depth of the recessed portion corresponds to a thickness variation of an upper layer of the semiconductor topography between said first and second portions.
Dependencies are inferred from the claim text.