US 6,785,877 B1 · Standard cell, standard cell array, and system and method for placing and routing standard cells

Abstract

In a placement and routing for a standard cell type LSI design, each standard cell comprises a VDD power supply terminal formed of a P-type diffused layer, a VSS power supply terminal formed of an N-type diffused layer, and an input terminal and an output terminal formed of a first level metal. A plurality of standard cells are located to form a standard cell array, and VDD and VSS power supply lines formed of the first level metal are located to extend along opposite sides of the standard cell array, respectively. For connecting the power supply terminal of the standard cell to the power supply line of the first level metal, a power supply line formed of the diffused layer is extended from the power supply terminal to the power supply line of the first level metal, and a contact bole is formed at an overlapping portion between the power supply line of the first level metal and power supply line formed of the diffused layer. Thus, it is possible to place and route standard cells having different widths with no hindrance, and it is also possible to form an inter-cell connection in the device formation region between the power supply line and the wiring area within the cell. In addition, it is possible to set the width of the power supply line of the first level metal to an appropriate width for each standard cell array.

Claims6

Dependent claims

A standard cell placement and routing processing system comprising a library file which stores information of various standard cells each of which comprises a power supply terminal of a diffused layer, an input terminal of a first level metal and an output terminal of said first level metal, a circuit connection information file which stores circuit connection information of an LSI to be developed, a constraint information file which stores constraint information concerning the placement and the routing, a parameter file which stores parameter information including a power supply voltage and an operating frequency of said LSI to be developed and a sheet resistance of said diffused layer, a placement and routing system for executing the placement and the routing of standard cells selected in accordance with the circuit connection information from said circuit connection information file, by utilizing information from said library file, said constraint information file and said parameter file, and an input/output and display apparatus for displaying a history and a result of the placement and the routing and for externally inputting a control command to control said placement and routing system;

wherein said placement and routing system detects a signal line which becomes a hindrance in reducing the resistance of a power supply line, removes said signal line, and locates a connection path between said first level metal and a second level metal at an end position to which the removed signal line was connected.

A standard cell placement and routing method for executing a placement and routing of standard cells by using a standard cell placement and routing processing system which comprises a library file which stores information of various standard cells each of which comprises a power supply terminal of a diffused layer, an input terminal of a first level metal and an output terminal of said first level metal, a circuit connection information file which stores circuit connection information of an LSI to be developed, a constraint information file which stores constraint information concerning the placement and the routing, a parameter file which stores parameter information including a power supply voltage and an operating frequency of said LSI to be developed and a sheet resistance of said diffused layer, a placement and routing system for executing the placement and the routing of standard cells selected in accordance with the circuit connection information from said circuit connection information file, by utilizing information from said library file, said constraint information file and said parameter file, and an input/output and display apparatus for displaying a history and a result of the placement and the routing and for externally inputting a control command to control said placement and routing system, the method comprising:

a first step of reading out said circuit connection information from said circuit connection information file;
a second step of reading out from said cell library file, standard cells corresponding to the read-out circuit connection information, and locating the read-out standard cells into a plurality of standard cell arrays, each of said plurality of standard cell arrays including at least one substrate contact cell inserted for every a predetermined number of standards cells, and said standard cells included in each of said plurality of standard cell arrays being arranged in such a manner that respective well boundary lines within the standard cells in each standard cell array are aligned on one straight line in a plan view;
a third step of routing signal lines between the standard cells included in said standard cell array, in accordance with said circuit connection information;
a fourth step of extracting a contour of a wiring area of said signal lines within said standard cell array, and placing a power supply line at the outside of said wiring area;
a fifth step of forming a contact hole at an overlapping portion between said power supply line and said power supply terminal of said diffused layer within said standard cell in said standard cell array, or alternatively, extending a power supply line of said diffused layer from said power supply terminal to said power supply line when said power supply terminal does not overlap said power supply line, and then, forming a contact hole at an overlapping portion between said power supply line and said power supply line of said diffused layer;
a sixth step of discriminating whether or not the resistance of said power supply line of said diffused layer is not greater than a predetermined resistance value stored in said constraint information file;
a seventh step of re-routing said signal lines between said standard cells when it is discriminated in said sixth step that the resistance of said power supply line of said diffused layer is greater than said predetermined resistance value, and then, returning to said fourth step;
and
an eighth step of routing a not-connected interconnection in said standard cell array and signal lines between said standard cell arrays when it is discriminated in said sixth step that the resistance of said power supply line of said diffused layer is not greater that said predetermined resistance value.

6 more elements

a first step of reading out said circuit connection information from said circuit connection information file;
a second step of reading out from said cell library file, standard cells corresponding to the read-out circuit connection information, and locating the read-out standard cells into a plurality of standard cell arrays, each of said plurality of standard cell arrays including at least one substrate contact cell inserted for every a predetermined number of standards cells, and said standard cells included in each of said plurality of standard cell arrays being arranged in such a manner that respective well boundary lines within the standard cells in each standard cell array are aligned on one straight line in a plan view;
a third step of routing signal lines between the standard cells included in said standard cell array, in accordance with said circuit connection information;
a fourth step of extracting a contour of a wiring area of said signal lines within said standard cell array, and placing a power supply line at the outside of said wiring area;
a fifth step of forming a contact hole at an overlapping portion between said power supply line and said power supply terminal of said diffused layer within said standard cell in said standard cell array, or alternatively, extending a power supply line of said diffused layer from said power supply terminal to said power supply line when said power supply terminal does not overlap said power supply line, and then, forming a contact hole at an overlapping portion between said power supply line and said power supply line of said diffused layer;
a sixth step of discriminating whether or not the resistance of said power supply line of said diffused layer is not greater than a predetermined resistance value stored in said constraint information file;
a seventh step of re-routing said signal lines between said standard cells when it is discriminated in said sixth step that the resistance of said power supply line of said diffused layer is greater than said predetermined resistance value, and then, returning to said fourth step;
and
an eighth step of routing a not-connected interconnection in said standard cell array and signal lines between said standard cell arrays when it is discriminated in said sixth step that the resistance of said power supply line of said diffused layer is not greater than said predetermined resistance value;
wherein said seventh step includes:
a first sub-step of detecting a signal line which becomes a hindrance in reducing the resistance of said power supply line formed of said diffused layer to not greater than said predetermined resistance value;
a second sub-step of removing said signal line which becomes said hindrance, and providing a through-hole for connecting between said first level metal and a second level metal at an end position to which the removed signal line was connected;
and
a third sub-step of discriminating whether or not the resistance of said power supply line formed of said diffused layer shortened as the result of the removal of said signal line is not greater than said predetermined resistance value, and returning to said first sub-step when the resistance is greater than said predetermined resistance value, or alternatively completing said seventh step when the resistance is not greater than said predetermined resistance value.

11 more elements

a first step of reading out said circuit connection information from said circuit connection information file;
a second step of reading out from said cell library file, standard cells corresponding to the read-out circuit connection information, and provisionally locating the read-out standard cells into a plurality of provisional standard cell arrays;
a third step of dividing said provisional standard cell array into a plurality of cell groups each including not greater than a predetermined number of standard cells which are located adjacent to one another;
a fourth step of selecting one cell group to be processed, from said plurality of cell groups;
a fifth step of routing signal lines between said standard cells within said one selected cell group, in accordance with the circuit connection information from said circuit connection information file;
a sixth step of extracting a contour of a wiring area of said signal lines within said one selected cell group, to register a power supply line inhibit area in said constraint information file;
a seventh step of placing a power supply line along the outside of said power supply line inhibit area within said one selected cell group;
an eighth step of forming a contact hole at an overlapping portion between said power supply line and said power supply terminal of said diffused layer within said standard cell in said one selected cell group, or alternatively, extending a power supply line of said diffused layer from said power supply terminal to said power supply line when said power supply terminal does not overlap said power supply line, and then, forming a contact hole at an overlapping portion between said power supply line and said power supply line of said diffused layer;
a ninth step of discriminating whether or not the resistance of said power supply line of said diffused layer is not greater than a predetermined resistance value stored in said constraint information file;
a tenth step of re-routing said signal lines between said standard cells when it is discriminated in said ninth step that the resistance of said power supply line of said diffused layer is greater than said predetermined resistance value, and then, returning to said fifth step;
an eleventh step of discriminating whether or not the processing for all the cell groups has been completed, when it is discriminated in said ninth step that the resistance of said power supply line of said diffused layer is not greater than said predetermined resistance value, and then, returning to said fourth step when the processing for all the cell groups has not yet been completed;
a twelfth step of replacing said provisional standard cell array composed of the provisionally located standard cells, with corresponding cell groups processed above, when it is discriminated in said eleventh step that the processing for all the cell groups has been completed;
a thirteenth step of interconnecting respective power supply lines of said cell groups processed above to form a power supply line for said standard cell array;
and
a fourteenth step of routing a not-connected interconnection in said standard cell array and signal lines between said standard cell arrays.

12 more elements

Dependencies are inferred from the claim text.

Standard cell, standard cell array, and system and method for placing and routing standard cells

Life of this patent

Standard cell, standard cell array, and system and method for placing and routing standard cells

Life of this patent

Abstract

Claims6