Testing vias and contacts in an integrated circuit
AssigneeXilinx, Inc.
InventorsTai-An Chao, Zicheng Gary Ling, Shihcheng Hsueh
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Abstract
A test arrangement is designed to test whether one in a chain of vias or contacts has abnormally high resistance. The arrangement contains a plurality of via or contact chains and a plurality of decoders. The chains are switchably connected to a resistance measurement device. Each decoder has a unique address such that it will generate a control signal when a predetermined address is address thereon. The control signal is used to close a switch, which connect one of the chains to the resistance measurement device. By sequentially applying different addresses to the decoders, the resistance of the chains can be individually measured.
Claims7
A circuit arrangement on a semiconductor wafer for identifying defects associated with fabrication of the semiconductor wafer, the circuit arrangement comprising a plurality of test circuits, each test circuit comprising:
- a chain of connected vias or contacts;
- an addressable decoder associated with the chain of connected vias or contacts and having a set of address lines;
- and
- a first switch controlled by the decoder to selectively connect the chain of connected vias or contacts to a first terminal of a resistance measurement device.
Dependencies are inferred from the claim text.