Thermal processing of metal alloys for an improved CMP process in integrated circuit fabrication

memory device comprising:

• an array of memory cells;
• internal circuitry;
• and
• metal contacts and interconnects coupled to the memory cells and internal circuitry, wherein the metal contacts and interconnects are formed by annealing the memory at a temperature sufficient to drive alloy dopants into solid solution and quenching the memory prior to polishing the memory device to remove portions of a metal layer and form the metal contacts and interconnects.

A memory device, comprising:

• an array of memory cells;
• internal circuitry;
• a system metal alloy contacts and interconnects coupled to the memory cells and internal circuitry, the metal contacts and interconnects comprising a metal alloy layer with alloy dopants residing in contact vias and interconnect trenches formed in an insulating layer atop a substrate;
• and
• wherein the metal alloy layer is annealed a first time to drive the alloy dopants into solid solution, quenched to prevent the alloy dopants from coming out of solution, and annealed a second time after polishing to allow the dopants to come out of solution in order to increase the conductivity of the metal alloy layer.

A memory device, comprising:

• an array of memory cells;
• internal circuitry;
• vias and interconnect trenches formed within an insulating layer atop the substrate and connected to the internal circuitry and array of memory cells;
• and
• a high-conductivity doubly annealed metal alloy formed in the vias and interconnection trenches, wherein the high-conductivity doubly annealed metal alloy includes a metal alloy first annealed for driving alloy dopants into solid solution, quenched for preventing the alloy dopants from coming out of solid solution, polished for planarizing the metal alloy, and second annealed for allowing dopants to come out of solution.

A memory device comprising:

• an array of memory cells;
• internal circuitry;
• a high-conductivity system of contacts and interconnects coupled to the internal circuitry and array of memory cells, the high-conductivity system comprising:
• a layer of insulating material atop a substrate;
• vias formed in the insulating material extending down to the substrate at different locations;
• interconnect trenches formed in the insulating material, with each interconnect trench connected to at least one via;
• and
• high-conductivity means formed in the vias and interconnect trenches for providing a high-conductivity electrical connection between the different locations on the substrate, wherein the high-conductivity means includes a metal alloy first annealed for driving alloy dopants into solid solution, quenched for preventing the alloy dopants from coming out of solid solution, polished for planarizing the metal alloy, and second annealed for allowing dopants to come out of solution.

A memory device comprising:

• an array of memory cells;
• internal circuitry:
• high-conductivity system of contacts and interconnects coupled to the internal circuitry and array of memory cells, the high-conductivity system comprising:
• a layer of insulating material atop a substrate:
• vias formed in the insulating material extending down to the substrate at different locations;
• interconnect trenches formed in the insulating material, with each interconnect trench connected to at least one via;
• and
• high-conductivity means formed in the vias and interconnect trenches for providing a high-conductivity electrical connection between the different locations on the substrate, wherein the high-conductivity means includes a metal alloy first annealed at a first temperature to drive alloy dopants into solid solution to make the metal alloy more polishable, quenched to prevent the alloy dopants from coming out of solid solution, polished to planarize the metal alloy, and then second annealed at a second temperature such that dopants are allowed to come out of solution to increase the conductivity of the metal alloy.

A memory device comprising:

• an array of memory cells;
• internal circuitry;
• a substrate base layer with an insulating layer formed thereon;
• a layer of aluminum alloy residing in vias and interconnect trenches formed in the insulating layer, the metal alloy layer coupled to the array of memory cells and internal circuitry;
• and
• wherein the layer of aluminum alloy is annealed at a first anneal temperature between 400° C. and 500° C., quenched for preventing alloy dopants from coming out of solid solution, polished for planarizing the layer of aluminum alloy, and annealed at a second anneal temperature less than the first anneal temperature.