US 6,784,510 B1 · Magnetoresistive random access memory device structures

Abstract

A method for fabricating an MRAM device structure includes providing a substrate on which is formed a first transistor and a second transistor. An operative memory element device is formed in electrical contact with the first transistor. At least a portion of a false memory element device is formed in electrical contact with the second transistor. A first dielectric layer is deposited overlying the at least a portion of a false memory element device and the operative memory element device. The first dielectric layer is etched to simultaneously form a first via to the at least a portion of a false memory element device and a second via to the operative memory element device. An electrically conductive interconnect layer is deposited so the electrically conductive interconnect layer extends from the at least a portion of a false memory element device to the operative memory element device.

Claims18

Dependent claims

A magnetoresistive random access memory device structure comprising:

a semiconductor substrate having a first transistor and a second transistor disposed therein;
an operative magnetic tunnel junction element device electrically coupled to said first transistor;
at least a portion of a false magnetic tunnel junction element device electrically coupled to said second transistor;
and
a metal interconnect layer extending from said at least a portion of a false magnetic tunnel junction element device to said operative magnetic tunnel junction element device.

2 more elements

A magnetoresistive random access memory device comprising a plurality of electrically coupled arrays of magnetic memory elements, each array comprising:

a semiconductor substrate having a first transistor and a plurality of second transistors therein;
a first interconnect stack formed on said semiconductor substrate and coupled to a terminal of said first transistor;
a plurality of second interconnect stacks formed on said semiconductor substrate, each second interconnect stack coupled to a terminal of one of said plurality of second transistors;
a plurality of operative magnetic tunnel junction element devices, each one of said plurality of operative magnetic tunnel junction element devices in electrical contact with one of said plurality of second interconnect stacks;
at least a portion of a false magnetic tunnel junction element device electrically coupled to said first interconnect stack;
and
a metal interconnect layer extending from said at least a portion of a false magnetic tunnel junction element device to each of said plurality of operative magnetic tunnel junction element devices.

4 more elements

Dependencies are inferred from the claim text.

Magnetoresistive random access memory device structures

Life of this patent

Magnetoresistive random access memory device structures

Life of this patent

Abstract

Claims18