Circuit and method for an integrated charged device model clamp

An integrated circuit comprising:

• a semiconductor substrate;
• a first drain region disposed in said substrate;
• a first channel region disposed in said substrate directly adjacent to said first drain region;
• a first gate dielectric overlying said first channel region;
• a first gate overlying said first gate dielectric;
• a first source region disposed in said substrate directly adjacent to said first channel region;
• a second channel region disposed in said substrate directly adjacent to said first source region and on a side of said first source region opposite to said first channel region;
• a second gate dielectric overlying said second channel region;
• a second gate overlying said second gate dielectric;
• a second drain region disposed in said substrate directly adjacent to said second channel region;
• and
• an input/output pad electrically coupled to said first gate and to said second drain region.

A method of forming an integrated circuit, said method comprising:

• a first drain region in a semiconductor substrate;
• forming a first source region in said substrate separated from said first drain region solely by a first channel region;
• forming a second drain region in said substrate separated from said first source region solely by a second channel region, wherein said second channel region is a different region than said first channel region;
• forming a first gate dielectric overlying said first channel region and a second gate dielectric overlying said second channel region;
• forming a first gate overlying said first gate dielectric and a second gate overlying said second gate dielectric;
• and
• forming an input/output pad on said semiconductor substrate electrically coupled to said first gate and to said second drain region.