Methods for manufacturing semiconductor devices and semiconductor devices

A method for manufacturing a semiconductor device, the method comprising the steps of:

• (a) forming a gate dielectric layer;
• (b) forming a first conductive layer on the gate dielectric layer;
• (c) forming an upper layer on the first conductive layer, at least a lower portion of the upper layer comprising a material different from at least an upper portion of the first conductive layer;
• (d) forming sidewall spacers on side walls of the first conductive layer and the upper layer;
• (e) forming an insulation layer that covers the upper layer and the sidewall spacers;
• (f) planarizing the insulation layer until an upper surface of the upper layer is exposed;
• (g) removing the upper layer to form a recessed section between the sidewall spacers on the upper portion of the first conductive layer;
• and
• (h) forming a second conductive layer in the recessed section to form a gate electrode that includes at least the first conductive layer and the second conductive layer.

A method for manufacturing a semiconductor device, the method comprising:

• forming a gate dielectric layer;
• forming a first conductive layer on the gate dielectric layer;
• forming an upper layer on the first conductive layer, the upper layer comprising a material different from that of the first conductive layer;
• forming sidewall spacers on side walls of the first conductive layer and the upper layer;
• removing the upper layer to form a recessed section between the sidewall spacers and above at least part of the first conductive layer;
• and
• forming a second conductive layer in the recessed section to form a gate electrode comprising the at least part of the first conductive layer and the second conductive layer.

A method for manufacturing a semiconductor device, the method comprising:

• forming a gate dielectric layer on a silicon substrate;
• forming a first conductive layer on the gate dielectric layer;
• forming a first upper layer comprising a silicon nitride layer on the first conductive layer;
• forming a second upper layer comprising a polysilicon layer on the first upper layer, wherein the first upper layer is positioned between the first conductive layer and the second upper layer;
• patterning and etching the first conductive layer, the first upper layer and the second upper layer so that the first conductive layer, the first upper layer and the second upper layer all have an identical width defined by side end surfaces;
• after the patterning and etching, forming sidewall spacers on the side end surfaces of the first upper conductive layer, the first upper layer and the second upper layer;
• after the forming sidewall spacers, forming an insulation layer over the second upper layer and the sidewall spacers;
• planarizing the insulation layer until an upper surface of the second upper layer is exposed;
• after the planarizing, removing the second upper layer and removing the first upper layer from between the sidewall spacers, while at least part of the first conductive layer remains between the sidewall spacers, wherein the removing the second upper layer and the removing the first upper layer forms an opening between the sidewall spacers;
• and
• forming a second conductive layer in the opening between the sidewall spacers to form a gate electrode that includes at least the first conductive layer and the second conductive layer.