Process to improve the Vss line formation for high density flash memory and related structure associated therewith

A method of forming a NOR-type flash memory, comprising:

• forming isolation regions in a surface of a semiconductor substrate in a core region, the isolation region extending in a bit line direction;
• forming memory cell layers over the semiconductor substrate in the core region, the memory cells layers overlying the isolation regions;
• patterning the memory cell layers to form a plurality of flash memory cells in an array, wherein the array comprises a plurality of bit line columns extending in the bit line direction and a plurality of word line rows extending in a word line direction which traverses the bit line direction;
• forming source and drain regions in the semiconductor substrate associated with each of the flash memory cells in the array, wherein the source regions are separated from one another by the isolation regions along the word line direction;
• forming a first dielectric layer over the flash memory cells in the core region, thereby covering the source and drain regions in the semiconductor substrate;
• forming a plurality of contact holes through the first dielectric layer down to a plurality of source regions of memory cells along a given word line;
• forming a trench in the first dielectric layer extending along the word line direction to the plurality of contact holes;
• filling the plurality of contact holes and the trench with a conductive material, thereby electrically coupling the plurality of source regions along the given word line together;
• forming a second dielectric layer over the first dielectric layer, and the conductive material in the contact holes and the trench.

A NOR-type flash memory cell structure, comprising:

• an array of flash memory cells arranged in columns of bit lines and rows of word lines, respectively, wherein each of the flash memory cells comprise a drain region and a source region, and where the source regions of flash memory cells along a word line are separated from one another by isolation regions;
• a first dielectric layer overlying the array of flash memory cells;
• and
• a conductive common source line embedded within the first dielectric layer and extending both in the word line direction and down and making conductive contact to the source regions of the flash memory cells along the word line direction, thereby electrically coupling together the source regions to form a substantially low resistance common source line.

A NOR-type flash memory cell structure, comprising:

• an array of flash memory cells arranged in columns of bit lines and rows of word lines, respectively, wherein each of the flash memory cells comprise a drain region and a source region;
• a first dielectric layer overlying the array of flash memory cells;
• and
• a conductive common source line embedded within the first dielectric layer and extending down and making conductive contact to the source regions of the flash memory cells, thereby electrically coupling together the source regions to form a substantially low resistance common source line, wherein the conductive common source line comprises a plurality of conductive contacts extending through the first dielectric layer to the source regions, and a plurality of first generally laterally extending conductive common source structures extending between source regions along respective word lines, thereby coupling together source regions along the respective word lines.

A method of forming a NOR-type flash memory array, comprising:

• forming an array of flash memory cells arranged in columns of bit lines and rows of word lines, respectively, wherein each of the flash memory cells comprise a drain region and a source region;
• forming a first dielectric layer over the array of flash memory cells;
• and
• embedding a conductive common source structure within the first dielectric layer, wherein the conductive common source structure extends along the word line direction makes contact down to the source regions of the flash memory cells and electrically couples the separated source regions together along the given word line to form a common source of the array.