Flash memory device and a method for fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsYou-Cheol Shin, Jong-Woo Park, Jung-Dal Choi
Life of this patent
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Abstract
A flash memory having a charge-storage dielectric layer and a method for forming the same are provided. According to one embodiment, charge-storage dielectric layers are formed over the first and second active regions. The charge-storage layer over the first active region is not connected to the charge-storage layer over the second active region. A gate line overlies the charge-storage layer and extends across the first and second active regions and the isolation region. The charge-storage layer can be formed only where a gate line intersects an active region of a semiconductor substrate, not on an isolation region. Thus, undesirable influence or disturbance from adjacent memory cells can be avoided.
Claims17
A method for forming a flash memory device, comprising:
- sequentially forming a charge-storage dielectric layer and an etching mask layer on a semiconductor substrate;
- patterning the etching mask layer and the charge-storage layer, thereby exposing regions of the semiconductor substrate;
- forming isolation regions in the exposed regions of the semiconductor substrate, the isolation regions defining active regions;
- removing the patterned etching mask layer;
- forming an upper conductive layer overlying the patterned charge-storage layer;
- and
- patterning the upper conductive layer and the patterned charge-storage layer, thereby forming a gate line intersecting the isolation regions and the active regions.
A method for forming a flash memory comprising:
- sequentially forming a charge-storage dielectric layer, a lower conductive layer, and an etching mask layer on a semiconductor substrate;
- patterning the etching mask layer, the lower conductive layer, and the charge-storage dielectric layer, thereby exposing regions of the semiconductor substrate;
- etching the exposed regions of the semiconductor substrate to form trenches therein;
- filling the trenches with a trench-filling insulating layer;
- planarizing the trench-filling insulating layer until the patterned etching mask layer is exposed, thereby forming isolation regions defining active regions therebetween;
- removing the exposed patterned etching mask layer;
- forming an upper conductive layer on the isolation regions and the patterned lower conductive layer;
- and
- patterning the upper conductive layer, the patterned lower conductive layer, and the patterned charge-storage layer, thereby forming gate lines intersecting the isolation regions and active regions.
A method for forming flash memory device comprising:
- forming a charge-storage layer on a semiconductor substrate;
- patterning the charge-storage layer to expose regions of the semiconductor substrate,
- forming isolation regions in the exposed regions of the semiconductor substrate, the isolation regions defining active regions therebetween, the patterned charge-storage layer self-aligned with the isolation regions;
- forming a conductive layer overlying the patterned charge-storage layer;
- and
- patterning the conductive layer and the patterned charge-storage layer to form gate lines overlying the patterned charge-storage layer, the gale lines extending across the active regions.
A method for fanning a flash memory device, comprising:
- sequentially forming a lower oxide layer, a nitride layer, an upper oxide layer (ONO layer) as a charge-storage layer and an etching mask layer an a semiconductor substrate;
- patterning the etching mask layer and the ONO layer, thereby exposing regions of the semiconductor substrate;
- etching the exposed regions of the semiconductor substrate to form trenches therein, and filling the trenches with a trench-filling insulating layer to form trench isolation regions defining active regions;
- removing the patterned etching musk layer;
- and
- forming an upper conductive layer and the patterned ONO layer, thereby forming a gate line intersecting the trench isolation regions and the active regions.
Dependencies are inferred from the claim text.