Method to form self-aligned split gate flash with L-shaped wordline spacers

A method to form split gate flash memory cells in the manufacture of an integrated circuit device comprising:

• providing a substrate;
• forming a pairs of floating gates overlying said substrate;
• forming common source plugs overlying said substrate and filling spaces between said floating gate pairs;
• forming an oxide layer overlying said substrate, said floating gates, and said common source plugs;
• depositing a polysilicon layer overlying said oxide layer;
• forming first dielectric spacers on vertical surfaces of said conductor layer;
• thereafter etching through said conductor layer where not covered by said first dielectric spacers to thereby form word line gates adjacent to said floating gates;
• and
• implanting ions into said substrate to form bit line drains self-aligned to said word line gates;
• forming second dielectric spacers on vertical surfaces of said word line gates and said first dielectric spacers;
• depositing a metal layer overlying said word line gates, said bit line drains, said first dielectric spacers, said second dielectric spacers, and said oxide layer;
• annealing said metal layer to form silicide regions on said word line gates and said bit line drains;
• and
• thereafter removing unreacted said metal layer to complete said split gate flash memory cells.

A split gate flash memory cell device comprising:

• a substrate;
• a pair of floating gates overlying said substrate;
• a common source plug overlying said substrate and filling spaces between said floating gate pair;
• a pair of word line gates each comprising:
• a polysilicon layer overlying said substrate and adjacent to one of said floating gates with an oxide layer therebetween;
• a first dielectric spacer on a vertical surface of said polysilicon layer;
• and
• a second dielectric spacer on a vertical surface of said polysilicon layer and of said first dielectric spacer;
• and
• a pair of bit line drains self-aligned to said word line gates.