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AssigneeFreescale Semiconductor, Inc.
InventorsKirk J. Strozewski, Kevin D. Lucas, Marc J. Olivares, Chi-Min Yuan
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A method (10) for correcting lithography error includes generating (18) data that defines relationships between at least one predetermined design layout parameter and a known minimum required lithographic process capability (e.g. minimum feature spacing), and then using the data to upsize (30) predetermined isolated features or portions of predetermined isolated or semi-isolated features. In some embodiments, the resulting wafer circuit pattern (70) has isolated features (71, 72, 74) that are all larger than a predetermined minimum width. The upsized features are larger in the wafer circuit pattern (70) than they are drawn in a designed database. The method for correcting the lithography error, in some embodiments, is stored on a computer readable storage medium.
A method for correcting lithography error, comprising:
A computer readable storage medium for storing a method for correcting lithography error, comprising:
Dependencies are inferred from the claim text.