High-speed, multiple-bank, stacked, and PCB-mounted memory module
OwnerHarrison Geneinventor
Life of this patent
Estimating the term…
Abstract
The density for any generation of Standard In-Line Memory Module (SIMM), or Dual In-Line-Memory Module (DIMM), chipset used to provide computer Random Access Memory (RAM), can be multiplied by surface-mounting multiple banks of SIMMs or DIMMs, where each bank occupies one side of a printed-circuit board (PCB) and at least a second PCB is connected to a first PCB, which is in turn connected through the standard edge connectors to the bus, with the banks connected through shared and controlled input-and-output lines, and wherein a single standard controller directs address-oriented storage to the corresponding portion of the stacked and connected banks.
Claims6
A device for increasing random access memory density for a computer for a given generation of Random Access Memory chips each having a plurality of connecting pins, comprising:
- a first printed circuit board, having a front side, a back side, an edge connector on its bottom edge, a first part of an I/O connector to a second printed circuit board, a clock, an I/O controller, a plurality of supporting connectors, and a plurality of Random Access Memory chips mounted on said first printed circuit board;
- said second printed circuit board having a front side, a back side, a second part of said I/O connector to said first printed circuit board that engages said first part of an I/O connector, a connector to a clock circuit, a connector to said I/O controller, attachments for a plurality of supporting connectors, and a plurality of Random Access Memory chips mounted on said second printed circuit board, said second printed circuit board being physically attached to said first printed circuit board by both said I/O connector and said supporting connectors;
- a pin layout and printed circuit leads on each said printed circuit board for said plurality of memory chips providing a unique input and output connection through said printed circuit leads between each pin of each said memory chip and said edge connector sufficient to address each separable memory address of said memory chips;
- each said printed circuit board also having printed circuit leads connecting through said I/O connector and said I/O controller in such fashion that one half (½) of said I/O leads are shared by both printed circuit boards and are controlled by said I/O controller;
- a connection between said clock circuit, said I/O controller, and each memory chip providing timing control for all operations;
- and,
- circuitry within said I/O controller enabling or disabling access to each of said first printed circuit board and second printed circuit board, said I/O controller further selecting the memory chip upon the selected printed circuit board to activate and connect to said edge connector, for a particular I/O operation requested by the computer.
A device for increasing random access memory density for a computer for a given generation of Random Access Memory chips each having a plurality of connecting pins, comprising:
- a first printed circuit board, having a front side, a back side, an edge connector on its bottom edge, a first part of an I/O connector to a second printed circuit board, a clock, an I/O controller, a plurality of supporting connectors, and a plurality of pairs of Random Access Memory chips mounted on said first printed circuit board such that one element of each pair of memory components is stacked atop a second element of each pair;
- said second printed circuit board having a front side;
- a back side, a second part of said I/O connector to said first printed circuit board that engages said first part of an I/O connector, a connector to a clock circuit, a connector to said I/O controller, attachments for a plurality of supporting connectors, and a plurality of pairs of Random Access Memory chips mounted on said second printed circuit board such that one element of each pair of memory components is stacked atop a second element of each pair, said second printed circuit board being physically attached to said first printed circuit board by both said I/O connector and said supporting connectors;
- a pin layout and printed circuit leads on each said printed circuit board for said plurality of pairs of memory chips providing a unique input and output connection through said printed circuit leads between each pin of each said memory chip and said edge connector sufficient to address each separable memory address of said memory chips;
- each said printed circuit board also having printed circuit leads connecting through said I/O connector and said I/O controller in such fashion that one half (½) of said I/O leads are shared by both printed circuit boards and are controlled by said I/O controller;
- a connection between said clock circuit, said I/O controller, and each memory chip providing timing control for all operations;
- and,
- circuitry within said I/O controller enabling or disabling access to each of said first printed circuit board and second printed circuit board, said I/O controller further selecting the memory chip upon the selected printed circuit board to activate and connect to said edge connector, for a particular I/O operation requested by the computer.
Dependencies are inferred from the claim text.