High-speed, current driven latch

An oscillator circuit having an output, the output having a first state and a second state, the output being controllable by a first trigger signal and a second trigger signal, the oscillator circuit comprising:

• a SET circuit that includes a first latch transistor and a SET transistor;
• and
• a RESET circuit that includes a second latch transistor and a RESET transistor;
• wherein:
• one condition from the group consisting of the following is true:
• 1) at the first state, a current is conducted by the SET circuit wherein the SET circuit is maintained such that a first switching threshold is obtainable by using the first trigger signal, 2) at the second state, the current is conducted by the RESET circuit wherein the RESET circuit is maintained such that a second switching threshold is obtainable by using the second trigger signal, and 3) a combination of 1 and 2;
• one condition from the group consisting of the following is true:
• 1′) the base of the first latch transistor is coupled to the base of the SET transistor, 2′) the base of the second latch transistor is coupled to the base of the RESET transistor, and 3′) a combination of 1′ and 2′;
• and
• the oscillator circuit further comprises an oscillator capacitor coupled to the SET circuit, such that, at the first state, the capacitor is substantially charged, and at the second state the capacitor is substantially discharged.