Midplane apparatus
AssigneeTelica, Inc.
InventorsStephen A. Caldara, John St. Amand, John Hutchins, George Giordano
Life of this patent
Estimating the term…
Abstract
A chassis, in the form of a midplane design holds equipment that provides communication services. The midplane design enables cables to be attached to modules secured to the back of the midplane. The rear modules have a minimum of circuitry so as to render them the least likely to fail. The front modules house the majority of the electronics. The rear modules can route the interface signals to a card in the adjacent front slot, directly through the midplane.
Claims26
An electronic midplane assembly comprising:
- a plurality of front module slots on a first side of the assembly, and a plurality of corresponding rear module slots on a second side of the assembly, said front modules slots comprising a plurality of input/output (I/O) slots, a plurality of central processing unit (CPU)/Timing slots, a plurality of switching fabric (SF) slots, and a centrally located I/O slot;
- a first and second set of DC power pins for each of said front module slots for providing power thereto;
- for each of said plurality of I/O slots, a first and a second set of DS1 pins providing electrical communication from an I/O module to a corresponding rear module slot;
- for each of said plurality of I/O slots, a set of SF interconnect pins providing electrical communication to a set of SF traces that are in electrical communication with the SF slots;
- for each of said plurality of I/O slots, a set of DS3 pins providing electrical communication from the I/O module to the corresponding rear modules, the set of DS3 pins being located between said first and second sets of DS1 pins;
- a DS1 signal protection bus substantially spanning the length of the midplane assembly and separated into a first trace set in relay-controlled electrical communication with said first set of DS1 pins, and a second trace set in relay-controlled, electrical communication with said second set of DS1 pins;
- at least one DS3 signal protection bus having a first portion located below a vertical centerline of the midplane assembly and spanning from a first set of the module slots positioned nearer left and right edges of the midplane, and a second portion located above a vertical centerline of the midplane assembly and spanning from a second set of module slots positioned at a relative interior of the first set of module slots, said at least one DS3 signal protection bus being in relay-controlled electrical communication with the DS3 pins;
- and
- a set of utility pins for each front module, the utility pins being located below said second set of DS1 pins.
In a midplane assembly that supports a combination of 1:1 system processor redundancy, 1:1 timing source redundancy, 1:1 high speed internal communication redundancy, and support for at least two N:1 redundant external interfaces, and comprises:
- a plurality of front module slots on a first side of the assembly, and a plurality of corresponding rear module slots on a second side of the assembly, the front modules slots comprising a plurality of input/output (I/O) slots, a plurality of central processing unit (CPU)/Timing slots, a plurality of switching fabric (SF) slots, and a centrally located I/O slot;
- a first and second set of DC power pins for each of the front module slots for providing power thereto;
- for each of said plurality of I/O slots, a first and a second set of DS1 pins, a set of DS3 pins, and a set of SF pins;
- a DS1 signal protection bus substantially spanning the length of the midplane assembly and separated into a first trace set in relay-controlled electrical communication with said first set of DS1 pins, and a second trace set in relay-controlled electrical communication with said second set of DS1 pins;
- a DS3 signal protection bus having a first portion located below a vertical centerline of the midplane assembly and spanning from a first set of the I/O module slots positioned near left and right edges of the midplane assembly, and a second portion located above a vertical centerline of the midplane assembly and spanning from a second set of I/O module slots positioned at an interior relative to the first set of I/O module slots, the DS3 signal protection bus being in relay-controlled electrical communication with the set of DS3 pins;
- and a set of utility pins for each front module slot, an I/O module for the I/O slots comprising:
- a first and a second DC power connector that receives the first and second set of DC power pins, respectively;
- a combined DS1 and DS3 connector that receives the first set of DS1 pins and the set of DS3 pins;
- a switch fabric connector that receives the switch fabric pins;
- a DS1 connector located below a vertical centerline of the midplane assembly that receives the second set of DS1 pins;
- and
- a utility pin connector that receives the set of utility pins.
In a midplane assembly that supports a combination of 1:1 system processor redundancy, 1:1 timing source redundancy, 1:1 high speed internal communication redundancy, and support for at least two N:1 redundant external interfaces, and comprises a plurality of front module slots on a first side of the assembly, and a plurality of corresponding rear module slots on a second side of the assembly, the front modules slots comprising a plurality of input/output (I/O) slots, a plurality of central processing unit (CPU)/Timing slots, a plurality of switching fabric (SF) slots, and a centrally located I/O slot;
- a first and second set of DC power pins for each of said front module slots for providing power thereto;
- for each I/O module slot, a first and a second set of DS1 pins, and a first and second set of DS3 pins, a set of switch fabric pins;
- a third and fourth set of DS3 pins, and a third set of DS1 pins;
- a DS1 signal protection bus substantially spanning the length of the midplane assembly and separated into a first trace set in relay-controlled electrical communication with the first and second set of DS1 pins, and a second trace set in relay-controlled electrical communication with the third set of DS1 pins;
- a DS3 signal protection bus having a first portion located below a vertical centerline of the midplane assembly and substantially spanning from a first set of the I/O module slots positioned near left and right edges of the midplane assembly, and a second portion located above a vertical centerline of the midplane assembly and substantially spanning from a second set of I/O module slots positioned at an interior relative to the first set of I/O module slots, the DS3 signal protection bus being in relay-controlled electrical communication with each of the first, second, third and fourth set of DS3 pins;
- and a set of utility pins for each front module slot, a rear center I/O module for a rear center I/O slot comprising:
- a first and a second DC power connector that receives the first and second set of DC power pins, respectively;
- a first DS1 connector and second DS1 connector located above a vertical centerline of the midplane assembly the first DS1 connector and the second DS1 connector receiving the first and second set of DS1 pins, respectively, the second DS1 connector being located below the first DS1 connector;
- a first DS3 connector and second DS3 connector located above a vertical centerline of the midplane assembly the first DS3 connector and the second DS3 connector receiving the first and second set of DS3 pins, respectively;
- a third DS1 connector located below a vertical centerline of the midplane assembly that receives the third set of DS1 pins;
- a third DS3 connector and fourth DS3 connector located below a vertical centerline of the midplane assembly the third DS3 connector and the fourth DS3 connector receiving the third and fourth set of DS3 pins, respectively;
- a switch fabric connector positioned between the second and third DS1 connectors that receives the switch fabric pins;
- and
- a utility pin connector that receives the set of utility pins.
In a midplane assembly that supports a combination of 1:1 system processor redundancy, 1:1 timing source redundancy, 1:1 high speed internal communication redundancy, and support for at least two N:1 redundant external interfaces, and comprises a plurality of front module slots on a first side of the assembly, and a plurality of corresponding rear module slots on a second side of the assembly, the front modules slots comprising a plurality of input/output (I/O) slots, a plurality of central processing unit (CPU)/Timing slots, a plurality of switching fabric (SF) slots, and a centrally located I/O slot;
- a first and second set of DC power pins for each of said front module slots for providing power thereto;
- for each of said plurality of SF slots, a first set of maintenance pins, a first, second, third, and fourth set of SF interconnect pins, a second set of maintenance pins, and a set of pins to electrically connect a SF slot to a CPU/Timing slot, a SF module for each of the SF slots comprising:
- a first and a second DC power connector that receive first and second set of DC power pins, respectively;
- a first maintenance connector that receives the first set of maintenance pins;
- a first, a second, a third and a fourth SF connectors that receive the first, second, third and fourth SF pins, respectively;
- a second maintenance connector that receives the second set of maintenance pins;
- and
- a connector to provide an electrical connection to CPU/Timing slot pins.
In a midplane assembly that supports a combination of 1:1 system processor redundancy, 1:1 timing source redundancy, 1:1 high speed internal communication redundancy, and support for at least two N:1 redundant external interfaces, and comprises a plurality of front module slots on a first side of the assembly, and a plurality of corresponding rear module slots on a second side of the assembly, the front modules slots comprising a plurality of input/output (I/O) slots, a plurality of central processing unit (CPU)/Timing slots, a plurality of switching fabric (SF) slots, and a centrally located I/O slot;
- a first and second set of DC power pins for each of said front module slots for providing power thereto;
- for each CPU/Timing module slot, a set of pins for electrically connecting to a system clock, a set of pins for electrically connecting to a system synchronization signal, a set of pins to provide a common CPU I/O, and a set of pins to electrically connect one of said plurality of CPU/Timing slots to one of said plurality of SF slots, a CPU/Timing module for each of the CPU/Timing slots comprising:
- a first and a second DC power connector for receiving first and second set of DC power pins, respectively;
- a system clock connector that receives the set of system clock pins;
- a synchronization connector that receives the set of system synchronization pins;
- a CPU connector that receives the set of pins to provide a common CPU I/O;
- and
- a CPU/Timing connector that receives the set of pins to electrically connect one of said plurality of CPU/Timing slots to one of said plurality of SF slots.
Dependencies are inferred from the claim text.