Electrostatic discharge protection for a mixed-voltage device using a stacked-transistor-triggered silicon controlled rectifier

An integrated circuit, comprising:

• a signal pad for receiving and outputting a signal;
• a rectifier with an anode and a cathode including a first n-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first n-type portion, and a second n-type portion contiguous with the second p-type portion, wherein the anode of the rectifier is coupled to the signal pad;
• a first transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the first n-type portion of the rectifier;
• a second transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the second n-type portion of the rectifier, and the second terminal is coupled to the second terminal of the first transistor;
• and
• a voltage coupling circuit coupled to the gate terminals of the first and second transistors.

An integrated circuit, comprising:

• a signal pad for receiving and outputting a signal;
• an output buffer having a first terminal and a second terminal, wherein the second terminal is coupled to the signal pad;
• a rectifier, having an anode and a cathode, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first n-type portion, and a second n-type portion contiguous with the second p-type portion, wherein the first p-type portion is coupled to the anode, the second n-type portion is coupled to the cathode, the anode is coupled to the first terminal of the output buffer, and the cathode is coupled to ground;
• a first transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the first n-type portion of the rectifier;
• a second transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the second terminal of the first transistor, and the second terminal is coupled to the second n-type portion of the rectifier;
• and
• a voltage coupling circuit having a first terminal, a second terminal, a third terminal and a fourth terminal, wherein the first terminal is coupled to the anode of the rectifier, the second and the third terminals are respectively coupled to the gate terminals of the first and second transistor, and the fourth terminal is coupled to the cathode of the rectifier.

An integrated circuit, comprising:

• a signal pad for receiving and outputting a signal;
• an output buffer having a first terminal and a second terminal, wherein the second terminal is coupled to the signal pad;
• a rectifier with an anode and a cathode including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first n-type portion, and a second n-type portion contiguous with the second p-type portion, wherein the anode of the rectifier is coupled to the second terminal of the output buffer and the cathode of the rectifier is coupled to ground;
• a first transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the first n-type portion of the rectifier;
• a second transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the second terminal of the first transistor, and the second terminal is coupled to the second n-type portion of the rectifier;
• and
• a voltage coupling circuit having a first terminal, a second terminal, a third terminal and a fourth terminal, wherein the first terminal is coupled to the first terminal of the output buffer, the second and the third terminals are respectively coupled to the gate terminals of the first and second transistor, and the fourth terminal is coupled to the cathode of the rectifier.

A method for protecting an integrated circuit with a dual input/output pad from electrostatic discharge, comprising:

• providing a rectifier having a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first n-type portion, and a second n-type portion contiguous with the second p-type portion;
• providing a first transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the first n-type portion of the rectifier;
• providing a second transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the second terminal of the first transistor, and the second terminal is coupled to the second n-type portion of the rectifier;
• and
• providing a voltage coupling circuit coupled to the gate terminals of the first and second transistors.