Dual-triggered electrostatic discharge protection circuit

An electrostatic discharge protection circuit comprising:

• a clamping circuit including a first transistor, the first transistor having a drain, a source, a gate and a substrate;
• and
• a control circuit having a second transistor and at least one diode, said at least one diode having a first end and a second end, the second transistor being coupled to the first end of the at least one diode,
• wherein said control circuit is coupled to the clamping circuit, the control circuit being coupled to the gate and substrate of the first transistor and providing a first bias voltage signal to the gate of the first transistor and a second bias voltage signal to the substrate of the first transistor to trigger the clamping circuit to discharge an electrostatic current, and wherein the first bias voltage is less than the second bias voltage.

An integrated circuit, comprising:

• signal receiving means for receiving an electrostatic signal;
• clamping means for directing the electrostatic signal to ground, the clamping means having a first end and a second end, the first end being coupled to the signal receiving means and the second end being coupled to ground;
• and
• control means having a first transistor coupled to the clamping means for providing a first voltage signal and a second voltage signal to trigger the clamping means to direct the electrostatic signal to ground, a second transistor, and at least one diode having a first end and a second end, the first transistor being coupled to the first end of the at least one diode, and the second transistor being coupled to the second end of the at least one diode, wherein the first voltage signal is different from the second voltage signal.

An integrated circuit, comprising:

• signal receiving means for receiving an electrostatic signal;
• clamping means for directing the electrostatic signal to ground, the clamping means having a first end and a second end, the first end being coupled to the signal receiving means and the second end being coupled to ground;
• control means coupled to the clamping means for providing a first voltage signal and a second voltage signal to trigger the clamping means to direct the electrostatic signal to ground;
• and
• transient detection means coupled to the control means.

An integrated circuit, comprising:

• a signal pad;
• a clamping circuit including a first NMOS transistor having a drain, a source, a gate and a substrate, wherein the drain of the first NMOS transistor is coupled to the signal pad and the source of the first NMOS transistor is coupled to ground;
• and
• a control circuit having at least one transistor coupled to the gate and substrate of the first NMOS transistor and the signal pad, the control circuit providing a first bias voltage signal to the gate of the first NMOS transistor and a second bias voltage signal to the substrate of the first NMOS transistor to trigger the clamping circuit to discharge an electrostatic current, wherein the first bias voltage is greater than the second bias voltage.

An integrated circuit, comprising:

• a signal pad;
• a clamping circuit including a first NMOS transistor having a drain, a source, a gate and a substrate, wherein the drain of the first NMOS transistor is coupled to the signal pad and the source of the first NMOS transistor is coupled to ground;
• and
• a control circuit coupled to the gate and substrate of the first NMOS transistor and the signal pad, the control circuit providing a first bias voltage signal to the gate and a second bias voltage signal to the substrate, wherein the first bias voltage is less than the second bias voltage.

An integrated circuit, comprising:

• a signal pad;
• a clamping circuit including a first NMOS transistor having a drain, a source, a gate and a substrate, wherein the drain of the first NMOS transistor is coupled to the signal pad and the source of the first NMOS transistor is coupled to ground;
• and
• a control circuit having at least one transistor coupled to the gate and substrate of the first NMOS transistor and the signal pad, the control circuit providing a first bias voltage signal to the gate of the first NMOS transistor and a second bias voltage signal to the substrate of the first NMOS transistor to trigger the clamping circuit to discharge an electrostatic current,
• wherein the control circuit comprises a plurality of serially coupled diodes, and
• the at least one transistor including:
• a PMOS transistor having a source, a drain, a substrate and a gate, the source of the PMOS transistor being coupled to the signal pad, the drain of the PMOS transistor being coupled to a first of the plurality of serially coupled diodes;
• and
• a second NMOS transistor having a source, a drain, a gate, and a substrate, wherein the drain of the second NMOS transistor is coupled to a last of the serially coupled diodes, the source of the second NMOS transistor is coupled to ground, and the gate of the second NMOS transistor is coupled to the gate of the PMOS transistor.

An integrated circuit, comprising:

• a signal pad;
• a clamping circuit including a first PMOS transistor having a drain, a source, a gate and a substrate, wherein the drain of the first PMOS transistor is coupled to the signal pad and the source of the first PMOS transistor is coupled to a VDD signal;
• and
• a control circuit having at least one transistor coupled to the gate and substrate of the first PMOS transistor and the signal pad, the control circuit providing a first bias voltage signal to the gate of the first PMOS transistor and a second bias voltage signal to the substrate of the first PMOS transistor,
• wherein the control circuit comprises a plurality of serially coupled diodes, and
• the at least one transistor including:
• an NMOS transistor having a source, a drain, a substrate and a gate, the source of the NMOS transistor being coupled to the signal pad, the drain of the NMOS transistor being coupled to a first of the plurality of serially coupled diodes;
• and
• a second PMOS transistor having a source, a drain, a gate, and a substrate, wherein the drain of the second PMOS transistor is coupled to a last of the serially coupled diodes, the source of the second PMOS transistor is coupled to a VDD signal, and the gate of the second PMOS transistor is coupled to the gate of the NMOS transistor.

An integrated circuit, comprising:

• a signal pad;
• a first clamping circuit including a first PMOS transistor having a drain, a source, a gate and a substrate, wherein the drain of the first PMOS transistor is coupled to the signal pad and the source of the first PMOS transistor is coupled to a VDD signal;
• a first control circuit coupled to the gate and substrate of the first PMOS transistor and the signal pad, the first control circuit providing a first bias voltage signal to the gate of the first PMOS transistor and a second bias voltage signal to the substrate of the first PMOS transistor;
• a second clamping circuit including a first NMOS transistor having a drain, a source, a gate and a substrate, wherein the drain of the first NMOS transistor is coupled to the signal pad and the source of the first NMOS transistor is coupled to ground;
• and
• a second control circuit coupled to the gate and substrate of the first NMOS transistor and the signal pad, the control circuit providing a third bias voltage signal to the gate of the first NMOS transistor and a fourth bias voltage signal to the substrate of the first NMOS transistor.

An integrated circuit, comprising:

• a signal pad;
• a clamping circuit including a first PMOS transistor having a drain, a source, a gate and a substrate, wherein the drain of the first PMOS transistor is coupled to the signal pad and the source of the first PMOS transistor is coupled to a VDD signal;
• and
• a control circuit having at least one transistor coupled to the gate and substrate of the first PMOS transistor and the signal pad, the control circuit providing a first bias voltage signal to the gate of the first PMOS transistor and a second bias voltage signal to the substrate of the first PMOS transistor, wherein the control circuit provides the first bias voltage having a level greater than a level of the second bias voltage.

An integrated circuit, comprising:

• a signal pad;
• a clamping circuit including a first PMOS transistor having a drain, a source, a gate and a substrate, wherein the drain of the first PMOS transistor is coupled to the signal pad and the source of the first PMOS transistor is coupled to a VDD signal;
• and
• a control circuit having at least one transistor coupled to the gate and substrate of the first PMOS transistor and the signal pad, the control circuit providing a first bias voltage signal to the gate of the first PMOS transistor and a second bias voltage signal to the substrate of the first PMOS transistor, wherein the control circuit provides the first bias voltage having a level less than a level of the second bias voltage.