Stress migration test structure and method therefor

A chip, comprising:

• a substrate having circuits within an area for circuit layout;
• bond pads on the substrate along at least one edge of the chip, the bond pads being between the area for circuit layout and the at least one edge of the chip;
• and
• a stress migration test device fabricated as part of the chip, the stress migration test device comprising a conductive runner, the conductive runner having a length sufficient to develop axial stress above the threshold for nucleating voids for the technology in which the runner is fabricated, the conductive runner having a plurality of taps at uniform impedance intervals along the runner, the taps spaced along the runner such that the variation of impedance of the runner between adjacent taps due to presence of a stress migration void in the conductive runner is a detectable portion of the impedance between the adjacent taps absent stress migration voids.

A chip, comprising:

• a substrate having circuits within an area for circuit layout;
• bond pads on the substrate along at least one edge of the chip, the bond pads being between the area for circuit layout and the edge of the chip;
• and
• at least a portion of a stress migration test device fabricated between the bond pads and the at least one edge of the chip, the stress migration test device comprising a conductive runner, the conductive runner having a length sufficient to develop axial stress above the threshold for nucleating voids for the technology in which the runner is fabricated, the conductive runner having a plurality of taps at uniform impedance intervals along the runner, the taps spaced along the runner such that the variation of impedance of the runner between adjacent taps due to presence of a stress migration void in the conductive runner is a detectable portion of the impedance between the adjacent taps absent stress migration voids.

A chip, comprising:

• a substrate having circuits within an area for circuit layout;
• bond pads on the substrate along at least one edge of the chip, the bond pads being between the area for circuit layout and the at least one edge of the chip;
• and
• a stress migration test device fabricated as part of the chip, the stress migration test device comprising a conductive runner, the conductive runner having a length sufficient to develop axial stress above the threshold for nucleating voids for the technology in which the runner is fabricated, the conductive runner having a plurality of taps at impedance intervals along the runner, the taps spaced along the runner such that the variation of impedance of the runner between adjacent taps due to presence of a stress migration void in the conductive runner is a detectable portion of the expected impedance between the adjacent taps absent stress migration voids.

A chip, comprising:

• a substrate having circuits within an area for circuit layout;
• bond pads on the substrate along at least one edge of the chip, the bond pads being between the area for circuit layout and the edge of the chip;
• and
• at least a portion of a stress migration test device fabricated between the bond pads and the at least one edge of the chip, the stress migration test device comprising a conductive runner, the conductive runner having a length sufficient to develop axial stress above the threshold for nucleating voids for the technology in which the runner is fabricated, the conductive runner having a plurality of taps at impedance intervals along the runner, the taps spaced along the runner such that the variation of impedance of the runner between adjacent taps due to presence of a stress migration void in the conductive runner is a detectable portion of the expected impedance between the adjacent taps absent stress migration voids.

A method of determining the presence or absence of stress migration voids in a conductor, comprising the steps of:

• fabricating on a substrate a conductive runner having a length sufficient to develop axial stress above the threshold for nucleating voids for the technology in which the runner is fabricated;
• providing taps at equal impedance intervals along the runner;
• passing a known current through a first portion of the conductive runner between two spaced taps;
• measuring the voltage developed across a second portion of the conductive runner due to the known current, the second portion of the conductive runner being a subset of the first portion of the conductive runner;
• calculating an impedance of the second portion of the conductive runner;
• normalizing the impedance of the second portion of the conductive runner by a nominal impedance to generate an impedance ratio;
• and
• comparing the impedance ratio to an impedance ratio threshold to determine whether a stress migration void is present in the second portion of the conductive runner.

A method of determining the presence or absence of stress migration voids in a conductor, comprising the steps of:

• fabricating on a substrate a conductive runner having a length sufficient to develop axial stress above the threshold for nucleating voids for the technology in which the runner is fabricated;
• providing taps at impedance intervals along the runner;
• passing a known current through a first portion of the conductive runner between two spaced taps;
• measuring the voltage developed across a second portion of the conductive runner due to the known current, the second portion of the conductive runner being a subset of the first portion of the conductive runner;
• calculating an impedance of the second portion of the conductive runner;
• normalizing the impedance of the second portion of the conductive runner by an expected impedance for the second portion of the conductive runner to generate an impedance ratio;
• and
• comparing the impedance ratio to an impedance ratio threshold to determine whether a stress migration void is present in the second portion of the conductive runner.