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US 6,747,337 B1Granted
Semiconductor wafer with a dicing line overlapping a defect
AssigneeRenesas Technology Corp.
InventorsHidekazu Yamamoto, Yasuhiro Kimura
Life of this patent
Estimating the term…
Abstract
A dicing lines is placed to overlap a slip created in a wafer, so that the slip extends within the dicing line.
Claims8
A semiconductor wafer comprising a notch for recognition of crystal surface orientation, a pre-existing defect extending from said notch, and a dicing line, wherein
- said dicing line is aligned with said pre-existing defect extending from said notch, prior to cutting the wafer, such that the dicing line overlaps the defect.
A semiconductor wafer secured to a boat during high-temperature processing comprising a pre-existing defect extending from a contact point of said boat and said semiconductor wafer and a dicing line, wherein
- said dicing line is aligned with said preexisting defect extending from a contact point of said boat and said semiconductor wafer, prior to cutting the wafer, such that the dicing line overlaps the defect.
Dependencies are inferred from the claim text.