Method of manufacturing an integrated semiconductor device having a nonvolatile floating gate memory, and related integrated device

An integrated semiconductor device, comprising:

• at least one logic transistor and at least one nonvolatile floating gate memory cell, said memory cell comprising a first gate oxide layer over a silicon substrate, source and drain regions in said silicon substrate, a floating gate formed by a first polysilicon layer over said first gate oxide layer, a control gate formed by a second polysilicon layer;
• superimposed on said floating gate, and a dielectric layer interposed between said floating gate and said control gate and electrically insulating said floating gate and said control gate, said control gate completely covering said floating gate so that said control gate partially overlaps said source and drain regions without self-alignment;
• said logic transistor comprising a second gate oxide layer over said silicon substrate, a gate, formed by said second polysilicon layer, superimposed on said second gate oxide layer, said second gate oxide layer having a different thickness than a thickness of said first gate oxide layer.

An integrated circuit device, comprising a logic transistor, a memory cell, and a high voltage transistor, the memory cell having a floating gate and a control gate and the high voltage transistor having a lower gate and an upper gate, the floating gate and the lower gate comprising a first polysilicon layer formed on a first gate oxide, the control gate and the upper gate comprising a second polysilicon layer formed on a second gate oxide, the logic transistor having a gate comprising the second polysilicon layer formed on the second gate oxide, the second gate oxide having a thickness different than the thickness of the first gate oxide.