Vertical gate conductor with buried contact layer for increased contact landing area
AssigneeInternational Business Machines Corporation
InventorThomas W. Dyer
Life of this patent
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Abstract
An access transistor for a semiconductor device includes a gate disposed in an upper region of a deep trench formed within a substrate of the semiconductor device. A gate contact is formed atop the gate, the gate contact having a diameter less than that of the deep trench and the gate. A conductive layer surrounds the gate contact, the conductive layer being disposed over the deep trench and over an active area of the semiconductor device surrounding the deep trench. The conductive layer provides a effective contact landing area for a diffusion region formed in the active area, wherein the effective contact landing area further includes a region between the diffusion region and the gate contact.
Claims14
An access transistor for a semiconductor device, comprising:
- a gate disposed in an upper region of a deep trench, said deep trench formed within a substrate of the semiconductor device;
- a gate contact formed atop said gate, said gate contact having a diameter less than that of said deep trench and said gate;
- and
- a conductive layer surrounding said gate contact, said conductive layer disposed over said deep trench and over an active area of the semiconductor device surrounding said deep trench;
- wherein said conductive layer provides a effective contact landing area for a diffusion region formed in said active area, said effective contact landing area further including a region between said diffusion region and said gate contact.
A memory cell for a dynamic random access memory (DRAM) array, compromising:
- a storage capacitor formed within a lower region of a deep trench;
- and
- a vertical access transistor coupled with said storage capacitor, said vertical access transistor further comprising:
- a gate disposed in an upper region of said deep trench;
- a gate contact formed atop said gate, said gate contact having a diameter less than that of said deep trench and said gate;
- and
- a conductive layer surrounding said gate contact, said conductive layer disposed over said deep trench and over an active area of the semiconductor device surrounding said deep trench;
- wherein said conductive layer provides a effective contact landing area for a bitline diffusion formed in said active area, said effective contact landing area further including a region between said bitline diffusion and said gate contact.
Dependencies are inferred from the claim text.