Method of fabricating a vertical quadruple conduction channel insulated gate transistor

A method of fabricating a vertical insulated gate transistor, the method comprising:

• forming a vertical semiconductor pillar with one or more flanks on a semiconductor substrate;
• forming a dielectrically isolated semiconductor gate with a cavity, so that the gate is resting on the flanks of the pillar and on the substrate;
• wherein the step of forming the vertical semiconductor pillar includes forming a primary semiconductor pillar resting on the substrate and forming the cavity in the primary pillar
• wherein the forming of the primary semiconductor pillar further includes:
• forming a stack including a first layer of a first semiconductor material, a second layer of a second semiconductor material that can be selectively eliminated with respect to the first material, and a third layer of the first semiconductor material;
• forming on the stack a surface semiconductor layer of the first material;
• and
• selectively etching in the second layer of the stack to form the cavity;
• wherein the step of forming the gate further includes coating one or more internal walls of the cavity with an isolating layer and filling the cavity with a gate material so as to form between a portion of the gate situated in the cavity and a portion of the gate resting on the flanks of the pillar, and to form two connecting semiconductor regions extending between a source region and a drain region of the transistor.