Methods of fabbricating a stack-gate non-volatile memory device and its contactless memory arrays

A method of fabricating a stack-gate non-volatile memory device and its contactless memory array, comprising the steps of:

• providing a semiconductor substrate of a first conductivity type;
• forming alternately a plurality of STI regions and a plurality of active regions on said semiconductor substrate, wherein each of the plurality of STI regions is filled with a first raised field-oxide layer and each of the plurality of active regions has a first conductive layer being formed on a first gate-dielectric layer;
• forming sequentially an intergate-dielectric layer, a second conductive layer, and a second masking dielectric layer over a flat surface being alternately formed by said first raised field-oxide layer and said first conductive layer to form a stack-gate structure;
• patterning said stack-gate structure by using a masking photoresist step to define a plurality of stack-gate regions transversely to the plurality of STI regions;
• wherein each of the plurality of stack-gate regions is formed between a common-source region and a common-drain region;
• removing sequentially said second masking dielectric layer, said second conductive layer, and said intergate-dielectric layer and then etching anisotropically said first conductive layer in said common-source/drain regions to form a plurality of tapered floating-gate layers in each of the plurality of stack-gate regions;
• forming a plurality of common-source/drain diffusion regions of a second conductivity type in each of said common-source/drain regions by implanting doping impurities across said first gate-dielectric layers and the plurality of tapered floating-gate layers into surface portions of said semiconductor substrate in a self-aligned manner;
• removing said first gate-dielectric layers outside of the plurality of tapered floating-gate layers and etching simultaneously said first raised field-oxide layers in each of said common-source/drain regions to form exposed semiconductor-substrate surfaces and second raised field-oxide layers;
• forming a first sidewall dielectric layer over each sidewall of the plurality of tapered floating-gate layers, a second sidewall dielectric layer over each sidewall of said second conductive layers, and a second gate-dielectric layer over each of said exposed semiconductor-substrate surfaces;
• forming a planarized third conductive layer to fill a gap formed in each of said common-source/drain regions;
• etching back anisotropically said planarized third conductive layer to a depth approximately equal to or smaller than a top surface level of said second raised field-oxide layer to form common conductive electrodes in each of said common-source/drain regions;
• forming a thermal-oxide layer over each of said common conductive electrodes to remove possible conductive material over said second raised field-oxide layers;
• forming a pair of first sidewall dielectric spacers over sidewalls of nearby stack-gate regions and on side portions of a flat surface being formed alternately by said thermal-oxide layer and said second raised field-oxide layer;
• etching back sequentially said thermal-oxide layers, said common conductive electrodes, and said second gate-dielectric layers between the pair of first sidewall dielectric spacers to form source/drain-sidewall conductive electrodes in each of said common-source/drain regions, wherein said second raised field-oxide layers are simultaneously etched to form third raised field-oxide layers;
• forming a planarized fourth conductive layer to fill a gap in each of said common-source/drain regions;
• etching back said planarized fourth conductive layer to a level slightly below a top surface of said third raised field-oxide layers to form self-registered common-source/drain conductive islands being integrated with said source/drain-sidewall conductive electrodes and formed on the plurality of common-source/drain diffusion regions in each of said common-source/drain regions;
• forming a planarized thick-oxide layer over said third raised field-oxide layers and said self-registered common-source/drain conductive islands in each of said common-source/drain regions;
• depositing a first interconnect-metal layer over said planarized thick-oxide layers in each of said common-source/drain regions and said second masking dielectric layer in each of the plurality of stack-gate regions;
• and
• patterning and etching said first interconnect-metal layer to form a plurality of bit lines, wherein each of the plurality of bit lines being formed transversely to a plurality of word lines formed by elongated second conductive layers is defined by a masking dielectric layer being aligned above each of the plurality of active regions and two sidewall dielectric spacers being formed over sidewalls of said masking dielectric layer.

A method of fabricating a stack-gate non-volatile memory device and its contactless memory array, comprising the steps of:

• providing a semiconductor substrate of a first conductivity type;
• forming alternately a plurality of shallow-trench-isolation (STI) regions and a plurality of active regions on said semiconductor substrate, wherein each of the plurality of STI regions is filled with a first raised field-oxide layer and each of the plurality of active regions has a first conductive layer being formed on a first gate-dielectric layer;
• forming sequentially an intergate-dielectric layer, a second conductive layer, and a second masking dielectric layer over a flat surface being alternately formed by said first raised field-oxide layer and said first conductive layer to form a stack-gate structure;
• patterning said stack-gate structure by using a masking photoresist step to define a plurality of stack-gate regions transversely to the plurality of STI regions,
• wherein each of the plurality of stack-gate regions is formed between a common-source region and a common-drain region;
• removing sequentially said second masking dielectric layer, said second conductive layer, and said intergate-dielectric layer and then etching anisotropically said first conductive layer in each of said common-source/drain regions to form a plurality of tapered floating-gate layers in each of the plurality of stack-gate regions;
• forming a plurality of common-source diffusion regions in each of said common-source regions and a plurality of common-drain diffusion regions in each of said common-drain regions by separately implanting doping impurities across said first gate-dielectric layers and the plurality of tapered floating-gate layers into surface portions of said semiconductor substrate in a self-aligned manner;
• removing said first gate-dielectric layers outside of the plurality of tapered floating-gate layers and etching simultaneously said first raised field-oxide layers to form exposed semiconductor-substrate surfaces and second raised field-oxide layers in each of said common-source/drain regions;
• forming a first sidewall dielectric layer over each sidewall of the plurality of tapered floating-gate layers, a second sidewall dielectric layer over each sidewall of said second conductive layers, and a second gate-dielectric layer over each of the exposed semiconductor-substrate surfaces;
• forming a planarized third conductive layer to fill a gap in each of said common-source/drain regions;
• etching back anisotropically said planarized third conductive layer to a depth approximately equal to a top surface level of said second raised field-oxide layer to form common conductive electrodes in each of said common-source/drain regions;
• forming a thermal-oxide layer over each of said common conductive electrodes to remove possible conductive material over said second raised field-oxide layers in each of said common-source/drain regions;
• forming a pair of first sidewall dielectric spacers over sidewalls of nearby stack-gate regions and on side portions of a flat surface being formed alternately by said thermal-oxide layer and said second raised field-oxide layer in each of said common-source/drain regions;
• etching back anisotropically said second raised field-oxide layers between the pair of first sidewall dielectric spacers to a level approximately equal to a toy surface of said second gate-dielectric layer to form third raised field-oxide layers and removing simultaneously said thermal-oxide layers and then removing said common conductive electrodes to form source/drain-sidewall conductive electrodes in each of said common-source/drain regions;
• removing said second gate-dielectric layers and simultaneously etching said third raised field-oxide layers between the pair of first sidewall dielectric spacers to form a first flat bed in each of said common-source regions and a second flat bed in each of said common-drain regions;
• forming a planarized fourth conductive layer between the pair of first sidewall dielectric spacers and on each of said first/second flat beds;
• etching back said planarized fourth conductive layer to form a common-source/drain conductive bus line integrated with said source/drain-sidewall conductive electrodes in each of said common-source/drain regions;
• forming a planarized thick-oxide layer over each of said common-source/drain conductive bus lines;
• removing selectively said second masking dielectric layers said second conductive layers in the plurality of stack-gate regions by using anisotropic dry etching;
• forming a planarized fifth conductive layer over each of said second conductive layers in each of the plurality of stack-gate regions;
• depositing a first interconnect-metal layer over said planarized fifth conductive layer in each of the plurality of stack-sate regions and said planarized thick-oxide layer in each of said common-source/drain regions;
• and
• patterning and etching said interconnect-metal layer, said fifth conductive layers, and said second conductive layers simultaneously to form a plurality of word lines integrated with a plurality of planarized control-gate conductive islands, wherein each of the plurality of word lines being formed transversely to said common-source/drain bus lines is defined by a masking dielectric layer being aligned above each of the plurality of active regions and two sidewall dielectric spacers being formed over sidewalls of said masking dielectric layer.