A method of fabricating a complimentary metal oxide semiconductor (CMOS), device on a semiconductor substrate, featuring twin, super-steep retrograde (SSR), well regions formed in silicon shapes which in turn are obtained via two selective epitaxial growth procedures, comprising the steps of:
- forming a silicon dioxide shape on said semiconductor substrate with a first opening exposing a first portion of said semiconductor substrate designated as a P type metal oxide semiconductor (PMOS) region, to be used for a P channel type device of said CMOS device, and with a second opening exposing a second portion of said semiconductor substrate designated as an N type metal oxide semiconductor (NMOS) region, to be used for an N channel type device of said CMOS device;
- performing a first SEG procedure to selectively grow a first bottom silicon shape on said first portion of said semiconductor substrate, located in said PMOS region, and to selectively grow a second bottom silicon shape on said second portion of said semiconductor substrate, located in said NMOS region;
- performing a first ion implantation procedure to place N type dopants in said first bottom silicon shape, located in said PMOS region;
- performing a second ion implantation procedure to place P type dopants in said second bottom silicon shape, located in said NMOS region;
- performing a second SEG procedure to selectively grow a first top silicon shape on said first bottom silicon shape, resulting in a first composite silicon shape in said PMOS region, comprised of said first top silicon shape on said first bottom silicon shape, and to selectively grow a second top silicon shape on said second bottom silicon shape, resulting in a second composite silicon shape comprised of said second top silicon shape on said second bottom silicon shape;
- performing an anneal procedure to activate said N type dopants and to distribute N type dopants in said first composite silicon shape, resulting in an SSR N well region in said PMOS region, and to activate said P type dopants and to distribute said P type dopants in said second composite silicon shape, resulting in an SSR P well region in said NMOS region;
- growing a silicon dioxide gate insulator layer on the top surface of said first composite silicon shape and on the top surface of said second composite silicon shape;
- forming a first gate structure on a portion of said silicon dioxide gate insulator layer located in said PMOS region, and forming a second gate structure on a portion of said silicon dioxide gate insulator layer located in said NMOS region;
- forming an N type pocket region in said PMOS region, in a portion of said first composite silicon shape not covered by said first gate structure, wherein the dopant level of said N type pocket region is greater than the N type doping level in said SSR N well region;
- forming a P type pocket region in said NMOS region, in a portion of said second composite silicon shape not covered by said second gate structure, wherein the dopant level of said P type pocket region is greater than the P type dopant level in said SSR P well region;
- forming a P type lightly doped source/drain region in a portion of said N type pocket region in said PMOS region;
- forming an N type lightly doped source/drain region in a portion of said P type pocket region in said NMOS region;
- forming insulator spacers on the sides of gate structures;
- forming a heavily doped P type source/drain region in said PMOS region, in a portion of said first composite silicon shape not covered by said first gate structure or by insulator spacers;
- and
- forming a heavily doped N type source/drain region in said NMOS region, in a portion of said second composite silicon shape not covered by said second gate structure or by insulator spacers.