Efficient redundancy calculation system and method for various types of memory devices

A method for analyzing failures for semiconductor memories comprising the steps of:

• providing a memory device including at least one memory chip, the at least one memory chip including a redundancy calculation region, the redundancy calculation region adapted to receive failure addresses of failed components, the redundancy calculation region further comprising:
• comparators for comparing the failure addresses to previous failure addresses to determine if new failures have been discovered,
• a memory for selectively storing addresses of failures,
• decision logic for determining if the memory device is fixable based on the new failures which have been discovered;
• testing the at least one memory chip to determine failure addresses of failed components on each memory chip;
• inputting the addresses of the failed components to the redundancy calculation region;
• comparing the failure addresses to previous failure addresses stored in the redundancy calculation region by employing the comparators;
• if a match exists between the previous failure addresses and the failure addresses, terminating the failure addresses which match and incrementing a match count, otherwise storing the failure addresses in the redundancy calculation region;
• and
• if the match count meets a threshold value, designating a must repair event to repair the component using redundancies.

A system for analyzing failures for semiconductor memories comprising:

• a self testing memory device including at least one memory chip adapted to determine failure addresses of failed components on the at least one memory chip, the at least one memory chip including a redundancy calculation region;
• the redundancy calculation region adapted to receive failure addresses of failed components, the redundancy calculation region further comprising:
• comparators for comparing the failure addresses to previous failure address to determine if new failures have been discovered, said failure addresses compared by said comparators comprising failure addresses not previously matched to a stored failure address;
• a memory for selectively storing address of failures which match previous failure addresses;
• and
• decision logic for determining if the memory device is fixable based on the new failures which have been discovered.