Method and apparatus for emulating a floating point stack in a translation process

In a processor which dynamically translates instructions programmed in a target instruction set to instructions in a host instruction set, a process for executing stack operations utilizing a plurality of explicitly-addressed registers comprising the steps of:

• executing a stack instruction utilizing selected ones of the explicitly-addressed registers,
• detecting any change in top-of-stack caused by the executed stack instruction,
• explicitly instructing a rotation of addresses of the selected ones of the plurality of explicitly-addressed registers by an amount depending on the change in top-of-stack, and
• comparing the top-of-stack with a predicted top-of-stack and selecting a translation of a next stack instruction for execution based upon the comparison.

Apparatus which dynamically translates instructions programmed in a target instruction set to instructions in a host instruction set and for executing instructions programmed for execution by a relatively-addressed stack comprising:

• a plurality of explicitly-addressed registers,
• a storage device capable of storing a top-of-stack address assigned to one of the explicitly-addressed registers with respect to which others of the plurality of explicitly-addressed registers are addressed,
• a computer-implemented software process for accruing changes in a top-of-stack address over a selected interval of instructions and generating an instruction to change a top-of-stack address held by the storage device, and for comparing a top-of-stack with a predicted top-of-stack and selecting a translation of a next stack instruction for execution based upon the comparison, and
• renaming circuitry responding to the instruction to combine a top-of-stack address held by the storage device and addresses relative to the top-of-stack of the explicitly-addressed registers.

A process for executing stack operations utilizing a plurality of explicitly-addressed registers in a host processor which dynamically translates instructions programmed in a target instruction set to instructions in a host instruction set comprising the steps of:

• executing a stack instruction utilizing selected ones of the explicitly-addressed registers,
• detecting any change in top-of-stack caused by the executed stack instruction,
• translating a next stack instruction assuming a top-of-stack at a predicted one of the explicitly-addressed registers without waiting to determine if top-of-stack is at the predicted one of the explicitly-addressed registers,
• comparing top-of-stack with predicted top-of-stack after rotation and before execution of the next stack instruction,
• executing the next stack instruction if top-of-stack and predicted top-of-stack compare, and
• selecting a different translation of the next stack instruction for execution if top-of-stack and predicted top-of-stack do not compare.