Semiconductor memory device having a double data rate (DDR) mode and utilizing a plurality of comparison circuits to prevent errors due to a late write function

A semiconductor memory device having a double data rate (DDR) mode in which it is possible to make an internal parallel operation on a specified memory address externally fed and a secondary memory address made different from said specified memory address by changing the last two or more bits, and an external serial input/output operation suitable with said internal parallel operation so that when an address comparing means of said semiconductor memory device detects that said specified memory address or said secondary memory address for a reading operation matches said specified memory address latched in an address register of said semiconductor memory device or said secondary memory address in a preceding writing operation, data corresponding to the matching memory address can be fed to the outside from a data register of said semiconductor memory device, wherein

• said address comparing means comprises:
• a first comparison logic circuit formed of combined circuits by which said last two or more bits of said specified memory address for a reading operation can be compared with said last two or more bits of said specified memory address for the preceding writing operation;
• a second comparison logic circuit formed of combined circuits that can detect if the bits other than said last two or more bits of said specified memory address for a reading operation respectively match the bits other than said last two or more bits of said specified memory address for the preceding writing operation;
• and
• a third comparison logic circuit formed of combined circuits which can detect that, when a match is obtained as the result from said second comparison logic circuit, said last two or more bits of said specified memory address or said secondary address for a reading operation match said last two or more bits of said specified memory address or said secondary memory address for the preceding writing operation, on the basis of the result from said first comparison logic circuit.