Back to results
US 6,725,185 B2Granted
Apparatus for modeling IC substrate noise
AssigneeCadence Design Systems, Inc.
InventorFrancois J. R. Clèment
Life of this patent
Estimating the term…
Abstract
Methods and apparatus for modeling noise present in an integrated circuit substrate are disclosed. A position on a surface of the integrated circuit substrate is obtained. A combination of layers associated with the position and defining a vertical column beneath the position is ascertained. A doping profile associated with the combination of layers is obtained. The doping profile includes a plurality of portions, each of which is associated with a different range of substrate depth. Noise in the integrated circuit substrate is then modeled using the obtained doping profile.
Claims28
A computer-readable medium storing thereon instructions for characterizing an integrated circuit substrate, comprising:
- instructions for obtaining a substrate doping profile, the substrate doping profile including a net doping level for each one of a plurality of depths within an integrated circuit substrate;
- instructions for obtaining a combination of layers associated with the substrate doping profile, the combination of layers being in an order in relation to a surface of the integrated circuit substrate;
- instructions for vertically discretizing the substrate doping profile to form a vertically discretized substrate doping profile;
- and
- instructions for associating the combination of layers with the vertically discretized substrate doping profile.
2 more elements
A computer-readable medium storing thereon computer-readable instructions for modeling noise present in an integrated circuit substrate, the method comprising:
- instructions for ascertaining a position on a surface of the integrated circuit substrate;
- instructions for obtaining a combination of layers associated with the position, the combination of layers defining a vertical column beneath the position;
- instructions for obtaining a doping profile associated with the combination of layers, wherein the doping profile comprises a plurality of portions, each of the portions associated with a different range of substrate depth;
- and
- instructions for modeling noise in the integrated circuit substrate using the obtained doping profile.
2 more elements
A computer-readable medium for modeling noise present in an integrated circuit substrate, the method comprising:
- instructions for ascertaining a position on a surface of the integrated circuit substrate;
- instructions for obtaining a combination of layers associated with the position, the combination of layers defining a vertical column beneath the position;
- instructions for obtaining a doping profile associated with the combination of layers, wherein the doping profile comprises a plurality of portions, each of the portions associated with a different range of substrate depth;
- instructions for obtaining a resistance at a junction between the position and an overlying layer;
- instructions for obtaining a capacitance at the junction between the position and the overlying layer;
- and
- instructions for modeling noise in the integrated circuit substrate using the obtained doping profile, the obtained resistance, and the obtained capacitance for the position.
4 more elements
A computer-readable medium for modeling noise present in an integrated circuit substrate, the method comprising:
- instructions for obtaining a plurality of substrate doping profiles for the integrated circuit substrate, each one of the plurality of substrate doping profiles including a net doping level for each one of a plurality of depths within an integrated circuit substrate;
- instructions for creating a plurality of subdivisions in each of the doping profiles such that each of the doping profiles comprises a plurality of portions, each of the portions being associated with a different range of substrate depth;
- instructions for ascertaining a position on a surface of the integrated circuit substrate;
- instructions for obtaining a combination of layers associated with the position, the combination of layers defining a vertical column beneath the position;
- instructions for obtaining a doping profile associated with the combination of layers;
- and
- instructions for ascertaining an equivalent resistance associated with each one of the plurality of portions in the obtained doping profile.
4 more elements
An apparatus for characterizing an integrated circuit substrate, comprising:
- means for obtaining a substrate doping profile, the substrate doping profile including a net doping level for each one of a plurality of depths within an integrated circuit substrate;
- means for obtaining a combination of layers associated with the substrate doping profile, the combination of layers being in an order in relation to a surface of the integrated circuit substrate;
- means for vertically discretizing the substrate doping profile to form a vertically discretized substrate doping profile;
- and
- means for associating the combination of layers with the vertically discretized substrate doping profile.
2 more elements
An apparatus for characterizing an integrated circuit substrate, comprising:
- a processor;
- and
- a memory, at least one of the processor and the memory being adapted for:
- obtaining a substrate doping profile, the substrate doping profile including a net doping level for each one of a plurality of depths within an integrated circuit substrate;
- obtaining a combination of layers associated with the substrate doping profile, the combination of layers being in an order in relation to a surface of the integrated circuit substrate;
- vertically discretizing the substrate doping profile to form a vertically discretized substrate doping profile;
- and
- associating the combination of layers with the vertically discretized substrate doping profile.
5 more elements
A computer system for modeling noise present in an integrated circuit substrate, the computer system comprising:
- a processor;
- and
- a memory having stored therein:
- instructions for ascertaining a position on a surface of the integrated circuit substrate;
- instructions for obtaining a combination of layers associated with the position, the combination of layers defining a vertical column beneath the position;
- instructions for obtaining a doping profile associated with the combination of layers, wherein the doping profile comprises a plurality of portions, each of the portions associated with a different range of substrate depth;
- and
- instructions for modeling noise in the integrated circuit substrate using the obtained doping profile.
5 more elements
An apparatus for modeling noise present in an integrated circuit substrate, the computer system comprising:
- means for ascertaining a position on a surface of the integrated circuit substrate;
- means for obtaining a combination of layers associated with the position, the combination of layers defining a vertical column beneath the position;
- means for obtaining a doping profile associated with the combination of layers, wherein the doping profile comprises a plurality of portions, each of the portions associated with a different range of substrate depth;
- and
- means for modeling noise in the integrated circuit substrate using the obtained doping profile.
2 more elements
A computer-readable medium storing thereon computer-readable instructions configured for modeling noise present in an integrated circuit substrate, comprising:
- instructions for ascertaining a position on a surface of the integrated circuit substrate;
- instructions for obtaining a combination of layers associated with the position, the combination of layers defining a vertical column beneath the position;
- instructions for obtaining a doping profile associated with the combination of layers, wherein the doping profile comprises a plurality of portions, each of the portions associated with a different range of substrate depth;
- instructions for obtaining a resistance at a junction between the position and an overlying layer;
- instructions for obtaining a capacitance at the junction between the position and the overlying layer;
- and
- instructions for modeling noise in the integrated circuit substrate using the obtained doping profile, the obtained resistance, and the obtained capacitance for the position.
4 more elements
An apparatus for modeling noise present in an integrated circuit substrate, comprising:
- a processor;
- and
- a memory, at least one of the processor and the memory being adapted for:
- ascertaining a position on a surface of the integrated circuit substrate;
- obtaining a combination of layers associated with the position, the combination of layers defining a vertical column beneath the position;
- obtaining a doping profile associated with the combination of layers, wherein the doping profile comprises a plurality of portions, each of the portions associated with a different range of substrate depth;
- obtaining a resistance at a junction between the position and an overlying layer;
- obtaining a capacitance at the junction between the position and the overlying layer;
- and
- modeling noise in the integrated circuit substrate using the obtained doping profile, the obtained resistance, and the obtained capacitance for the position.
7 more elements
An apparatus for modeling noise present in an integrated circuit substrate, comprising:
- means for ascertaining a position on a surface of the integrated circuit substrate;
- means for obtaining a combination of layers associated with the position, the combination of layers defining a vertical column beneath the position;
- means for obtaining a doping profile associated with the combination of layers, wherein the doping profile comprises a plurality of portions, each of the portions associated with a different range of substrate depth;
- means for obtaining a resistance at a junction between the position and an overlying layer;
- means for obtaining a capacitance at the junction between the position and the overlying layer;
- and
- means for modeling noise in the integrated circuit substrate using the obtained doping profile, the obtained resistance, and the obtained capacitance for the position.
4 more elements
A computer-readable medium storing thereon computer-readable instructions configured for modeling noise present in an integrated circuit substrate, comprising:
- instructions for obtaining a plurality of substrate doping profiles for the integrated circuit substrate, each one of the plurality of substrate doping profiles including a net doping level for each one of a plurality of depths within an integrated circuit substrate;
- instructions for creating a plurality of subdivisions in each of the doping profiles such that each of the doping profiles comprises a plurality of portions, each of the portions being associated with a different range of substrate depth;
- instructions for ascertaining a position on a surface of the integrated circuit substrate;
- instructions for obtaining a combination of layers associated with the position, the combination of layers defining a vertical column beneath the position;
- instructions for obtaining a doping profile associated with the combination of layers;
- and
- instructions for ascertaining an equivalent resistance associated with each one of the plurality of portions in the obtained doping profile.
4 more elements
An apparatus for modeling noise present in an integrated circuit substrate, comprising:
- means for obtaining a plurality of substrate doping profiles for the integrated circuit substrate, each one of the plurality of substrate doping profiles including a net doping level for each one of a plurality of depths within an integrated circuit substrate;
- means for creating a plurality of subdivisions in each of the doping profiles such that each of the doping profiles comprises a plurality of portions, each of the portions being associated with a different range of substrate depth;
- means for ascertaining a position on a surface of the integrated circuit substrate;
- means for obtaining a combination of layers associated with the position, the combination of layers defining a vertical column beneath the position;
- means for obtaining a doping profile associated with the combination of layers;
- and
- means for ascertaining an equivalent resistance associated with each one of the plurality of portions in the obtained doping profile.
4 more elements
An apparatus for modeling noise present in an integrated circuit substrate, comprising:
- a processor;
- and
- a memory, at least one of the processor and the memory being adapted for:
- obtaining a plurality of substrate doping profiles for the integrated circuit substrate, each one of the plurality of substrate doping profiles including a net doping level for each one of a plurality of depths within an integrated circuit substrate;
- creating a plurality of subdivisions in each of the doping profiles such that each of the doping profiles comprises a plurality of portions, each of the portions being associated with a different range of substrate depth;
- ascertaining a position on a surface of the integrated circuit substrate;
- obtaining a combination of layers associated with the position, the combination of layers defining a vertical column beneath the position;
- obtaining a doping profile associated with the combination of layers;
- and
- ascertaining an equivalent resistance associated with each one of the plurality of portions in the obtained doping profile.
7 more elements
Dependencies are inferred from the claim text.