Deterministic hardware behavior between multiple asynchronous clock domains through the novel use of a PLL
AssigneeHewlett-Packard Development Company, L.P.
InventorDavid Hartwell
Life of this patent
Estimating the term…
Abstract
A phase-locked loop (PLL) circuit is used to synchronize data transfers between a fast clock and a slow clock domain. The data transfer can be deterministic, where the fast clocks are generated by a first PLL and the slow clocks are generated by a second PLL. The second PLL is used to create a phase relationship between the first PLL output clock and a third PLL output clock. The phase relationship can provide for a deterministic data transfer.
Claims14
An apparatus to pass data between a fast clock domain and a slow clock domain comprising:
- a first phase-locked loop (PLL) circuit to receive a first reference clock and to generate a first clock for the fast clock domain;
- a first state machine to receive the first reference clock and a first divisor to generate a second reference clock, the first state machine further generates a fast to slow data transfer enable signal based on the first divisor;
- a second PLL circuit to receive the second reference clock and to generate a second clock for the slow clock domain, the second clock placed in fixed phase and edge relationship with the first clock;
- and
- a second state machine to receive the second clock and a second divisor to generate a feedback clock for the second PLL circuit and to generate a slow to fast data transfer enable signal based on the second divisor.
An apparatus to pass data between a fast clock domain and a slow clock domain comprising:
- a first phase-locked loop (PLL) circuit to receive a first reference clock and to generate a first clock for the fast clock domain;
- means for receiving the first reference clock and a first divisor to generate a second reference clock and further generating a fast to slow data transfer enable signal based on the first divisor;
- a second PLL circuit to receive the second reference clock and to generate a second clock for the slow clock domain, the second clock placed in fixed phase relationship with the first clock;
- and
- means for receiving the second clock and a second divisor to generate a feedback clock for the second PLL circuit and to generate a slow to fast data transfer enable signal based on the second divisor.
A computer system to pass data between a fast clock domain and a slow clock domain comprising:
- a processing unit to transmit a forwarding clock;
- an input/output (I/O) bridge that includes,
- a first phase-locked loop (PLL) circuit to receive the forwarding clock and to generate a first clock for the fast clock domain;
- a first state machine to receive the forwarding clock and a first divisor to generate a reference clock, the first state machine further generates a fast to slow data transfer enable signal based on the first divisor;
- a second PLL circuit to receive the reference clock and to generate a second clock for the slow clock domain, the second clock placed in fixed phase and edge relationship with the first clock;
- and
- a second state machine to receive the second clock and a second divisor to generate a feedback clock for the second PLL circuit and to generate a slow to fast data transfer enable signal based on the second divisor.
A method for passing data between a fast clock domain and a slow clock domain, the method comprising:
- providing a first phase-locked loop (PLL) circuit to receive a first reference clock and to generate a first clock for the fast clock domain;
- providing a first state machine to receive the first reference clock and a first divisor to generate a second reference clock, the first state machine further generates a fast to slow data transfer enable signal based on the first divisor;
- providing a second PLL circuit to receive the second reference clock and to generate a second clock for the slow clock domain, the second clock placed in fixed phase and edge relationship with the first clock;
- and
- providing a second state machine to receive the second clock and a second divisor to generate a feedback clock for the second PLL circuit and to generate a slow to fast data transfer enable signal based on the second divisor.
Dependencies are inferred from the claim text.