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US 6,724,686 B2Granted
Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode
AssigneeRenesas Technology Corp.
InventorsTsukasa Ooishi, Masatoshi Ishikawa
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Abstract
A synchronous semiconductor memory device operates an input/output buffer circuit in synchronization with an external clock signal in a single data rate SDRAM operation mode. In a double data rate SDRAM operation mode, an internal clock signal of a frequency two times that of the external dock signal is generated. The input/output buffer circuit is operated in synchronization with the internal dock signal.
Claims3
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells arranged in rows and columns;
- a control circuit controlling operation timing of said semiconductor memory device based on an external clock signal;
- an interface circuit, controlled by said control circuit, receiving a control signal from the outside of said semiconductor memory device;
- and
- a transmission timing change circuit changing transmission timing of said control signal to said memory cell array according to an operation mode.
2 more elements
Dependencies are inferred from the claim text.