Nonvolatile semiconductor memory device having selective multiple-speed operation mode

A nonvolatile semiconductor memory device comprising:

• a memory cell array formed of a plurality of cell array blocks each having a plurality of cell strings, each cell string formed with floating gate memory cell transistors having control gates respectively connected to a plurality of word lines, and wherein drain-source channels of the memory cell transistors are connected in series to each other between a string select transistor and a ground select transistor;
• a multiple-speed mode option part for generating a multiple-speed option signal;
• a row decoder for decoding a mat select address signal out of input row address signals in response to the multiple-speed option signal, and receiving the decoded mat select address signals and input row address signals to thereby generate row decoding signals for selecting during a multiple-speed mode operation a page size more than two times the page size of a default mode operation;
• a column address counter for generating column address signals that allow an antilogarithm counting operation to perform differently in response to a state of the multiple-speed signal;
• and
• a column decoder for decoding column address signals output from the column address counter to thereby generate column decoding signals for selecting during the multiple-speed mode operation a block size more than two times the block size of the default mode operation;
• and
• a page buffer controller for controlling operations of page buffers corresponding to the page and block sizes in response to a state of the multiple-speed signal.

A non-volatile memory device, comprising:

• a memory cell array formed of a plurality of cell array blocks each having a plurality of cell strings;
• a multiple-speed mode selector for generating a multiple-speed option signal, the multiple-speed option signal having at least a first state and a second state;
• and
• an address circuit structured to generate a first page size and block size for the memory cell array in response to the first state of the multiple-speed option signal, and structured to generate a second page size and block size for the memory cell array in response to the second state of the multiple-speed option signal.

A method for operating a memory device, comprising:

• generating a multiple-speed signal;
• sensing a state of the multiple-speed signal at an addressing circuit coupled to a memory array in the memory device;
• and
• changing page and block sizes of the memory cell array in response to the state of the multiple-speed option signal.