Method of recovering overerased bits in a memory device

A method of recovering overerased bits in a memory device following an erase operation, said method comprising:

• generating a first reference current in the memory device, said first reference current defining a highest current of a current window corresponding to a first reference level defining a state in which a memory cell is in an erased state;
• reading a plurality of memory cells to determine a first group of memory cells that have an amount of charge on its floating gate corresponding to a conduction current that is greater than the first reference current, said first group of memory cells being in an overerased state;
• applying a plurality of programming pulses to program each of the first group of memory cells to place an amount of charge on the floating gate of said cell until the conduction current is less than the first reference current, such that each of the first group of memory cells is programmed from the overerased state to the erased state;
• and
• applying a plurality of verify pulses to the specified memory cell, each one of said verify pulses being applied after each one of said programming pulses in an alternating manner.

A method of recovering overerased bits in a memory device following an erase operation, said method comprising:

• generating a first reference current and a second reference current in the memory device, said first reference current and said second reference current defining a current window defining a first reference level corresponding to a state in which a memory cell is in an erased state, said first reference current defining a highest current of the current window and said second reference current defining a lowest current of the current window;
• determining from a plurality of memory cells a first group of memory cells that have an amount of charge on its floating gate corresponding to a conduction current that is greater than the first reference current, said first group of memory cells being in an overerased state;
• applying a plurality of programming pulses to each of the first group of memory cells to place an amount of charge on the floating gate of said cell, said programming pulses increasing incrementally in voltage to increase the amount of charge on the floating gate at a steady rate until the conduction current is less than the first reference current, such that each of the first group of memory cells is programmed from the overerased state to the erased state;
• and
• applying a plurality of verify pulses to the specified memory cell, each one of said verify pulses being applied after each one of said programming pulses in an alternating manner.