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US 6,724,655 B2Granted
Memory cell using negative differential resistance field effect transistors
AssigneeProgressant Technologies, Inc.
InventorTsu-Jae King
Life of this patent
Estimating the term…
Abstract
A memory cell using both negative differential resistance (NDR) and conventional FETs is disclosed. A pair of NDR FETs are coupled in a latch configuration so that a data value passed by a transfer FET can be stored at a storage node. By exploiting an NDR characteristic, the memory cell can be implemented with fewer active devices. Moreover, an NDR FET can be manufactured using conventional MOS processing steps so that process integration issues are minimized as compared to conventional NDR techniques.
Claims16
A memory cell comprising:
- a transfer field effect transistor (FET), said transfer FET being configured to receive and/or transfer a data value from a data line to a storage node in response to a write and/or read signal respectively provided to the memory cell;
- and
- a first negative differential resistance (NDR) FET, said first NDR FET being configured to receive a first gate bias signal and having a first NDR FET source terminal coupled to said storage node, and a first NDR FET drain terminal coupled to a first voltage potential at a first node;
- and
- a second negative differential resistance (NDR) FET, said second NDR FET being configured to receive a second gate bias signal and having a second NDR FET drain terminal coupled to said storage node, and a second NDR FET drain terminal coupled to a second voltage potential at a second node;
- and
- wherein the memory cell uses said negative differential resistance characteristic of said first NDR FET and said second NDR FET to store said data value at said storage node.
4 more elements
A method of operating a memory cell having a storage node comprising the steps of:
- receiving or transferring a data value from a data line by gating a transfer field effect transistor (FET) in response to a write or read signal;
- and
- biasing a first negative differential resistance capable FET (first NDR FET) with a first bias signal so that said first NDR FET selectively operates with a first negative differential resistance (NDR) characteristic;
- and
- biasing a second negative differential resistance capable FET (second NDR FET) with a second bias signal so that said second NDR FET to operate with a first negative differential resistance (NDR) characteristic;
- and
- coupling said first NDR FET and said second NDR FET in a latched configuration with said transfer FET so that said data value can be read or written to the storage node in cooperation with said transfer FET;
- and
- operating said first NDR FET and said second NDR FET with said first NDR characteristic and said second NDR characteristic so that said data value is stored at said storage node.
6 more elements
Dependencies are inferred from the claim text.