US 6,724,592 B1 · Substrate-triggering of ESD-protection device

Abstract

Pin-to-pin electro-static-discharge (ESD) protection is provided for a bus-switch transistor that is connected to I/O pins at its source and drain. A p-type substrate is normally pumped below ground by a substrate bias generator when power is applied. However, during a pin-to-pin ESD test, power and ground are floating. A gate node is pulled high through a coupling capacitor by the ESD pulse. The gate node turns on a shunting transistor to couple the ESD pulse to the floating ground bus. The gate node also turns on a shorting transistor that connects the floating ground bus to the floating substrate. A resistor drains the coupling capacitor to the substrate, rather than to ground. Current is injected into the substrate by the resistor. The snapback voltage is lowered by substrate-triggering.

Claims20

Dependent claims

A pin-to-pin electro-static-discharge (ESD) protection device comprising:

an input node that receives an ESD pulse;
an internal ground bus;
a substrate node;
a coupling capacitor between the input node and a trigger node;
a shunting transistor having a gate connected to the trigger node, for conducting current between the input node and the internal ground bus during an ESD event;
a shorting transistor having a gate connected to the trigger node, for conducting current between the internal ground bus and the substrate node during the ESD event;
and
an injecting resistor, coupled between the trigger node and the substrate node, for injecting current into the substrate node during the ESD event, whereby portions of the ESD pulse are conducted to the internal ground bus and to the substrate node.

5 more elements

A bus-switch chip comprising:

a first input;
a second input;
a ground bus that is isolated from the first and second inputs;
bus-switch transistor means for conducting current between the first input and the second input when activated by an enable signal during normal operation;
first coupling means for coupling a portion of a first voltage shock applied to the first input to a first activating node;
first shunting means, responsive to the first activating node, for shunting current from the first input to the ground bus when the first coupling means couples the portion of the first voltage shock to the first activating node;
first shorting means, responsive to the first activating node, for shunting current from the ground bus to a substrate under the first shunting means and under the first shorting means when the first coupling means couples the portion of the first voltage shock to the first activating node;
and
second shunting means, responsive to a second activating node, for shorting the ground bus to the second input when the first coupling means couples the portion of the first voltage shock to the first activating node,
whereby the first shunting means and the first shorting means are activated by the first activating node.

7 more elements

An electro-static-discharge (ESD) protection circuit comprising:

an internal bus;
a bus-switch transistor having a gate driven by an enable signal, a drain coupled to a first input, a source coupled to a second input, and a substrate coupled to a substrate node;
a first capacitor between the first input and a first gate node;
a first shunt transistor having the first gate node as its gate, a drain coupled to the first input and a source coupled to the internal bus;
a first shorting transistor having the first gate node as its gate, a drain coupled to the internal bus and a source coupled to the substrate node;
a first cross-pin transistor having the first gate node as its gate, a drain coupled to the second input, and a source coupled to the substrate node;
and
injecting means, coupled between the first gate node and the substrate node, for injecting into the substrate node current from an ESD pulse applied to the first input.

5 more elements

Dependencies are inferred from the claim text.

Substrate-triggering of ESD-protection device

Life of this patent

Substrate-triggering of ESD-protection device

Life of this patent

Abstract

Claims20