Two-way shift register and image display device using the same

An image display device, comprising:

• a plurality of pixels formed at intersections of a plurality of data signal lines and a plurality of scanning lines;
• a data signal line driving circuit for consecutively driving said data signal lines, and
• a scanning signal line driving circuit for consecutively driving said scanning signal lines, wherein:
• at least one of said data signal line driving circuit and said scanning signal line driving circuit includes a shift register circuit including:
• a shift register section for switching an input side end to an output side end or vice versa in accordance with a switching signal, and for transferring an input signal through a plurality of flip-flops from the end that has become an input-side end to the end that has become an output-side end;
• and
• level shifters provided respectively adjacent to said ends of said shift register section such that said level shifter adjacent said end that has become an input-side end of said shift register section boosts a received signal and outputs the same as said input signal to an input at said end that has become an input-side end of said shift register section, while said level shifter adjacent to said end that has become an output-side end of said shift register section is stopped from operating to provide a boosted received signal to an input at said end that has become an output-side end of said shift register section.

An image display device, comprising:

• a plurality of pixels arrayed in a matrix;
• a plurality of data signal lines provided along rows of said pixels, respectively;
• a plurality of scanning signal lines provided along columns of said pixels, respectively;
• a scanning signal line driving circuit for applying scanning signals to said scanning signal lines one by one, respectively, at different timings in synchronization with a first clock signal having a predetermined frequency;
• and
• a data signal line driving circuit for extracting data signals to be applied to said pixels along said scanning signal lines to which the scanning signals are applied, from image signals that are consecutively applied in synchronization with a second clock signal having a predetermined frequency and that indicate display states of said pixels, respectively, and for outputting the extracted data signals to said data signal lines, respectively, wherein:
• at least one of the data signal line driving circuit and the scanning signal line driving circuit includes a two-way shift register that utilizes either the first clock signal or the second clock signal as a clock signal, that includes a plurality of flip-flops operating in synchronization with the clock signal, that is capable of switching a shift direction to either of two directions in accordance with a switching signal, and that is supplied with an input signal having an amplitude smaller than that of a driving voltage,
• wherein said two-way shift register further includes
• level shifters, each said level shifter being provided adjacent to and connected to an input at a different end of said flip-flops such that said level shifter adjacent to the end of said flip-flops supplied with said input signal boosts said input signal and outputs the same as said input signal to said flip-flops, while said level shifter not adjacent to the end of said flip-flops supplied with said input signal is stopped from operating to provide a boosted input signal to an input at the end of said flip-flops adjacent thereto.

A shift register comprising:

• a plurality of stages of flip-flops;
• and
• a first level shifter provided at one end of said plurality of stages of flip-flops and second level shifters provided at the other end of the plurality of stages of flip-flops, wherein:
• a shift direction is capable of being switched in both directions along said plurality of flip-flops according to a switching signal, and
• when the shift direction is designated so as to be a first direction, an input signal is boosted by the first level shifter provided at said one end of the plurality of stages of flip-flops so as to be applied to an input of a flip-flop at said one end and the second level shifter provided at said other end of the plurality of stages of flip-flops is stopped from operating to provide a boosted input signal to an input of a flip-flop at said other end, and
• when the shift direction is designated to be a second direction opposite to the first direction, an input signal is boosted by the second level shifter provided at said other end of the plurality of stages of flip-flops so as to be applied to an input of a flip-flop at said other end and the first level shifter provided at said one end of said plurality of stages of flip-flops is stopped from operating to provide a boosted input signal to the input of a flit-flop at said one end.

An image display device comprising a data signal line driving circuit and a scanning signal line driving circuit, wherein:

• at least either the data signal driving circuit or the scanning signal line driving circuit includes:
• a plurality of stages of flip-flops;
• and
• a first level shifter provided at one end of said plurality of stages of flip-flops and second level shifters provided at the other end of the plurality of stages of flip-flops, wherein:
• a shift direction is capable of being switched in both directions along said plurality of flip-flops according to a switching signal, and
• in a case where the shift direction is designated so as to be a first direction, an input signal is boosted by the first level shifter provided on a first end of the plurality of stages of flip-flops so as to be applied to an input of a flip-flop at the first end, and
• in a case where the shift direction is designated to be a second direction opposite to the first direction, the input signal is boosted by the second level shifter provided on a second end opposite to the first end of the plurality of stages of flip-flops so as to be applied to an input of a flip-flop at the second end.

An image display device, comprising:

• a plurality of pixels formed at intersections of a plurality of data signal lines and a plurality of scanning signal lines;
• a data signal line driving circuit for consecutively driving said data signal lines;
• and
• a scanning signal line driving circuit for consecutively driving said scanning signal lines, wherein:
• at least one of said data signal line driving circuit and said scanning signal line driving circuit includes a shift register circuit, said shift register circuit including:
• a shift register section for switching an input side end to an output side end or vice versa in accordance with a switching signal, and for transferring an input signal from the end that has become an input-side end to the end that has become an output-side end;
• and
• level shifters provided respectively adjacent to said ends of said shift register section such that said level shifter adjacent said end that has become an input-side end of said shift register section boosts a received signal and outputs the same as said input signal to an input at said end that has become an input-side end of said shift register section, while said level shifter adjacent to said end that has become an output-side end of said shift register section is stopped from operating to provide a boosted received signal to an input at said end that has become an output-side end of said shift register section.

An image display device, comprising:

• a plurality of pixels provided at intersections of a plurality of data signal lines and a plurality of scanning signal lines;
• a scanning signal line driving circuit for applying scanning signals to said scanning signal lines one by one, respectively, at different timings in synchronization with a first clock signal having a predetermined frequency;
• and
• a data signal line driving circuit for extracting data signals to be applied to said pixels along said scanning signal lines to which the scanning signals are applied, from image signals that are consecutively applied in synchronization with a second clock signal having a predetermined frequency and that indicate display states of said pixels, respectively, and for outputting the extracted data signals to said data signal lines, respectively, wherein:
• at least one of the data signal line driving circuit and the scanning signal line driving circuit includes a two-way shift register that utilizes either the first clock signal or the second clock signal as a clock signal, that includes a plurality of flip-flops operating in synchronization with the clock signal, that is capable of switching a shift direction to either of two directions in accordance with a switching signal, and that is supplied with an input signal having an amplitude smaller than that of a driving voltage,
• wherein said two-way shift register further includes
• level shifters, each said level shifter being provided adjacent to and connected to an input at a different end of said flip-flops such that said level shifter adjacent to the end of said flip-flops supplied with said input signal boosts said input signal and outputs the same as said input signal to said flip-flops, while said level shifter not adjacent to the end of said flip-flops supplied with said input signal is stopped from operating to provide a boosted input signal to an input at the end of said flip-flops adjacent thereto.

An image display device, comprising:

• a plurality of pixels provided at intersections of a plurality of data signal lines and a plurality of scanning signal lines;
• a scanning signal line driving circuit for applying scanning signals to said scanning signal lines one by one, respectively, in synchronization with a first clock signal having a predetermined frequency;
• and
• a data signal line driving circuit for extracting data signals to be applied to said pixels along said scanning signal lines to which the scanning signals are applied, from image signals that are consecutively applied in synchronization with a second clock signal having a predetermined frequency and that indicate display states of said pixels, respectively, and for outputting the extracted data signals to said data signal lines, respectively, wherein:
• at least one of the data signal line driving circuit and the scanning signal line driving circuit includes a two-way shift register that utilizes either the first clock signal or the second clock signal as a clock signal, that includes a plurality of flip-flops operating in synchronization with the clock signal, that is capable of switching a shift direction to either of two directions in accordance with a switching signal, and that is supplied with an input signal having an amplitude smaller than that of a driving voltage, and
• wherein said two-way shift register further includes
• level shifters, each said level shifter being provided adjacent to and connected to an input at a different end of said flip-flops such that said level shifter adjacent to the end of said flip-flops supplied with said input signal boosts said input signal and outputs the same as said input signal to said flip-flops, while said level shifter not adjacent to the end of said flip-flops supplied with said input signal is stopped from operating to provide a boosted input signal to an input at the end of said flip-flops adjacent thereto.